Abstract: A base die is configured to receive first data and first encoded data in a writing phase, perform first error checking and correction processing, wherein the first encoded data is obtained by performing a first error correction code encoding processing on the first data, and transmit second data to a memory die in the writing phase, wherein the second data includes a first data after the first error checking and correction processing; the base die is further configured to receive the second data from the memory die in a reading phase, perform second error correction code encoding processing on the second data to generate second encoded data, and transmit third data in the reading phase, wherein the third data includes the second encoded data and the first data after the first error checking and correction processing.

Abstract: A semiconductor testing structure forming method includes: a semiconductor substrate is provided, and the semiconductor substrate includes a plurality of active areas arranged separately; a first conductive wire is formed at a preset distance from the plurality of active areas in the semiconductor substrate, and the first conductive wire is connected with a substrate of a respective active device formed in each of the plurality of active areas; a plurality of first contact holes is formed on the first conductive wire; and a first metal layer is formed on top of each of the plurality of first contact holes to obtain the semiconductor testing structure, where the first metal layer is electrically connected with a first common pad and the first common pad is configured to perform an electric performance test on the semiconductor testing structure.

Abstract: A layout of a delay circuit unit, a layout of a delay circuit, and a semiconductor memory are provided. The layout of the delay circuit unit includes multiple layout units arranged in an array and each forming a NOT-AND (NAND) gate circuit; here several layout units conforming to a first layout pattern are sequentially arranged in a first row of the array; and several layout units conforming to a second layout pattern are sequentially arranged in a second row of the array; here the first layout pattern is different from the second layout pattern, and the first layout pattern and the second layout pattern are such that the first row and the second row form a center-symmetrical structure.

Abstract: A method for manufacturing a semiconductor structure includes: a first mask layer is formed on a dielectric layer, in which a first etching hole extending along a first direction parallel to the dielectric layer is formed in the first mask layer; a side of the first mask layer away from the dielectric layer is planarized; a second mask layer is formed on the first mask layer, in which a second etching hole extending along a second direction parallel to the dielectric layer is formed in the second mask layer, the first etching hole and the second etching hole constitute an etching hole; and the dielectric layer is etched along the etching hole to form the capacitor hole.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The manufacturing method of the semiconductor structure comprises: providing a substrate, comprising a polysilicon layer, a first conductive layer, a first dielectric layer, a mask layer, and a sacrificial layer sequentially formed thereon, wherein the sacrificial layer has a plurality of first trenches distributed at intervals; forming a first insulating layer on the sacrificial layer; forming a protective layer, the protective layer only covering a surface of the first insulating layer above the top surface of the sacrificial layer; removing the protective layer, part of the first insulating layer, the sacrificial layer, and part of the mask layer to form a first pattern layer; and removing part of the first dielectric layer, part of the first conductive layer, and part of the polysilicon layer by using the first pattern layer as a mask to form a BL structure.

Abstract: A semiconductor device includes a substrate, a gate oxide layer, a gate electrode and an injection region. The substrate includes a trench, a source region, a drain region and a channel region. The trench includes trench sidewalls and a trench bottom wall. The gate oxide layer is disposed in the trench. The gate oxide layer includes a groove. The gate electrode is disposed in the groove. The injection region is located on at least a side of the trench bottom wall, and at least a part of the injection region is closer to the drain region than the source region so that a threshold voltage at a portion of the channel region close to the injection region is less than a threshold voltage at a portion of the channel region far from the injection region.

Abstract: An anti-fuse device includes: a substrate; an anti-fuse gate, partially embedded in the substrate, a portion of the anti-fuse gate embedded in the substrate having one or more sharp corners; and an anti-fuse gate oxide layer, located between the anti-fuse gate and the substrate.

Abstract: A film deposition method and a film deposition apparatus are provided. The film deposition method includes: putting a substrate into a furnace tube, the furnace tube including a first section for placing the substrate, the first section having an inlet for reaction gas; heating, within a first preset time, a first heating module from a first initial temperature to a first preset temperature, the first heating module surrounding the first section and being configured to heat the first section; maintaining, within a second preset time, the first heating module continuously at the first preset temperature; and within a third preset time, introducing the reaction gas into the furnace tube from the inlet, and heating the first heating module from the first preset temperature to a second preset temperature so as to form a target film on a surface of the substrate placed in the first section.

Abstract: A local amplifier circuit includes write control transistors, configured to connect, based on write enable signal, global data line to local data line; column selection transistors, configured to connect, based on column selection signal, bit line to local data line; first control PMOS transistor having gate connected to local data line, one of source or drain connected to global data line, and the other one connected to read control transistor; and second control PMOS transistor having gate connected to complementary local data line, one of source or drain connected to complementary global data line, and the other one connected to read control transistor. Read control transistors are configured to pull up or down levels at terminals of first control PMOS transistor and second control PMOS transistor, each of which is source or drain connected to a respective one of read control transistors, to preset level based on read enable signal.

Abstract: A method and apparatus for testing a command are provided. The method includes that: when the test platform exists a target command to be sent to a memory, a duration of a deselect command is determined according to a minimum time interval between a target command and each of historical commands and the time when the each of the historical commands is sent and the present time; the target command is sent to the memory after the deselect command.

Abstract: Method for manufacturing a semiconductor device includes: forming a first area and a second area of a peripheral area on a substrate; forming a first lamination structure in the first area, and forming a second lamination structure in an array area and the second area; performing thermal treatment on the substrate so that atoms in a work function layer are diffused into a second dielectric layer, and an interface interaction occurs between the second dielectric layer and a first dielectric layer; removing the first lamination structure to the second dielectric layer, and removing the second lamination structure to the second dielectric layer; forming a fourth barrier layer and a second conductive layer, a content ratio of metallic element to non-metallic element in a first barrier layer being less than a content ratio of metallic element to non-metallic element in a second barrier layer and a third barrier layer.

Abstract: The present disclosure discloses a capacitor structure and its formation method and a memory. The method includes: providing a substrate; forming an electrode support structure on the substrate in a stacking fashion, wherein the electrode support structure includes at least a first support layer on its top, a capacitor hole is formed at intervals within the electrode support structure and extends upwards in a direction perpendicular to a surface of the substrate; forming, within the capacitor hole, an electrode post and an electrode layer extending from the electrode post to the upper surface of the first support layer; removing the electrode layer; removing the first support layer; forming a dielectric layer on the top of the electrode support structure, wherein the dielectric layer covers the top of the electrode post, and an outer peripheral wall of the top of the electrode post is connected with the dielectric layer.

Abstract: The present disclosure provides a comparator and a decision feedback equalization circuit. The comparator includes: a first sampling circuit provided with an output terminal, and configured to generate, under the control of a first control signal and a clock signal, a first differential signal according to a signal to be compared and a first reference signal; a second sampling circuit provided with an output terminal connected to the output terminal of the first sampling circuit, and configured to generate, under the control of a second control signal and the clock signal, a second differential signal according to the signal to be compared and a second reference signal, where the first reference signal is larger than the second reference signal.

Abstract: Some embodiments of the present application provide a photomask and its manufacturing method. The photomask includes: a substrate and a light shielding layer located on the substrate, an opening for exposing a surface of the substrate being formed in the light shielding layer; a barrier layer, the barrier layer covering a side wall of the opening and having its bottom contacted with the substrate.

Abstract: The present disclosure provides a manufacturing method for semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a substrate; forming first mask patterns and first mask openings on the substrate, the first mask opening being located between the adjacent first mask patterns; forming second mask patterns and second mask openings on the first mask patterns and the first mask openings, the second mask opening being located between the adjacent second mask patterns; and forming first patterns and first openings on the substrate based on the first mask patterns, the first mask openings, the second mask patterns and the second mask openings.

Abstract: A sense amplifier circuit includes: a charge module configured to charge a set signal node and a reset signal node according to a clock signal; and a sense module configured to sense and amplify a differential input signal according to the clock signal; where, the sense module includes a first amplification circuit, a second amplification circuit, and a cross hopping transfer circuit cross-connected between the first amplification circuit and the second amplification circuit. The cross hopping transfer circuit is configured to transfer a valid signal of a newly started amplification circuit to another amplification circuit if sensing is completed and the differential input signal hops, such that a set signal/reset signal remains unchanged. A flip-flop includes the sense amplifier circuit.

Abstract: Some examples of the present disclosure provide a method for manufacturing a wire layer. The method for manufacturing a wire layer includes steps in which a wafer having an opening is provided; conductive grains are deposited on the wafer, and on a bottom and a side wall of the opening to form a conductive film, during which a temperature of a surface of the wafer is lower than a flowing temperature of the conductive film, and when the temperature of the surface of the wafer is greater than or equal to the flowing temperature, the conductive film starting to flow; and after the conductive film is formed, the temperature of the surface of the wafer is elevated to perform a reflowing process, such that the conductive film is converted to a conductive layer filling up the opening.

Abstract: The present disclosure relates to the technical field of semiconductor manufacturing, and provides a semiconductor structure and a forming method thereof. The forming method includes: providing a semiconductor substrate, where a surface of the semiconductor substrate is provided with a plurality of conductive structures arranged at intervals; etching a surface of the conductive structure into a curved surface, and then depositing sequentially to form a first protective layer, a second protective layer and a third protective layer; etching the first protective layer, the second protective layer and the third protective layer to form a contact hole exposing the etched curved surface of the conductive structure; and forming a mask layer on a surface of the contact hole.

Abstract: An input sampling method includes the following operations. A first pulse signal and a second pulse signal are received. Logical operation is performed on the first pulse signal and the second pulse signal to determine a to-be-sampled signal. The to-be-sampled signal is obtained by shielding an invalid part of the second pulse signal according to a logical operation result. Sampling process is performed on the to-be-sampled signal to obtain a target sampled signal.

Abstract: The present disclosure relates to a method and apparatus for determining a signal margin (SM) of a memory cell, a storage medium and an electronic device, and relates to the technical field of integrated circuits. The method for determining an SM of a memory cell includes: when the memory cell performs write and read operations, determining a sense signal threshold of the memory cell under an influence of a noise; and determining, based on the sense signal threshold, an actual SM of the memory cell during data reading.