Abstract: A mark detection method includes: acquiring on-off information of marks on a photomask to be manufactured; comparing the on-off information with preset on-off information to determine whether the on-off information is consistent with the preset on-off information; and, correcting the on-off information according to the preset on-off information when it is determined that the on-off information is inconsistent with the preset on-off information. The mark detection method and apparatus and the computer-readable storage medium according to the present disclosure can automatically detect whether the on-off of marks is accurate, thereby improving the detection accuracy and reducing labor cost.

Abstract: A method for manufacturing the semiconductor structure includes following operations. A base is provided. A plurality of stack structures spaced apart from each other along a first direction are formed on a surface of the base and a plurality of first isolation layers arranged between the plurality of stack structures are formed, the plurality of stack structures include a plurality of first interlayer dielectric layers, a plurality of initial active layers and a plurality of second interlayer dielectric layers. Portion of each initial active layer is etched to form a first trench in each initial active layer. A plurality of oxide semiconductor layers are formed in a plurality of first trenches. Portions of the plurality of oxide semiconductor layers and remaining portions of the plurality of initial active layers are etched to form a plurality of active structures arranged in an array along the first direction and a second direction.

Abstract: An adjustment method for the chip output characteristics can include the following steps. When adjusting the output characteristics of the chip to be tested, first it is determined whether the output characteristics of the chip to be tested have been adjusted according to the state of each E-fuse. When determining that the output characteristics of the chip to be tested have not been adjusted, the target adjustment solution corresponding to the chip is determined among a plurality of adjustment solutions in a targeted manner according to the output performance of the chip to be tested. The E-fuse in the chip to be tested is subjected to blowing treatment according to the target adjustment solution, so as to adjust the output characteristics of the chip to be tested.

Abstract: The present application relates to a wafer processing device and a wafer processing method. The wafer processing device includes: a spraying unit configured to spray a photoresist-removing solution to remove a photoresist; and a heating unit mounted to the spraying unit and configured to heat the photoresist-removing solution to a preset temperature. According to the wafer processing device and wafer processing method of the present application, the photoresist-removing solution is heated to a preset temperature, so that the photoresist-removing solution dissolves the photoresist more rapidly and thoroughly. Therefore, the photoresist may be removed from a surface of the wafer more thoroughly, and further a yield of the wafer is increased.

Abstract: Provided are a sampling measurement method and system, computer device and storage medium. The sampling measurement method includes: acquiring a preset measurement ratio of each process element in a process station; acquiring an actual measurement ratio of a process element associated with a lot of products to be measured that arrive at the measurement station in the process station; and, when the actual measurement ratio of the associated process element is less than the corresponding preset measurement ratio, controlling a measurement machine at the measurement station to measure the lot of products to be measured.

Abstract: A method for manufacturing the semiconductor structure includes: providing a substrate, in which active regions and isolation regions are formed; forming grooves in the active regions, which include first grooves located at upper portions and second grooves located at lower portions and communicating with the first grooves, and a width of the first grooves is greater than a width of the second grooves; and forming gate structures in the first grooves and the second grooves.

Abstract: A semiconductor structure includes a substrate, a bit line, and a first isolation layer. A groove is set in the substrate. A bottom end of the bit line is set in the groove. The first isolation layer is at least partially set on a sidewall of the bit line, and the first isolation layer is in direct contact with the bit line.

Abstract: A optical proximity effect correction method includes: fabricating a test pattern mask according to design rules of a target pattern; obtaining data required by an optical proximity effect correction model, and establishing the optical proximity effect correction model; obtaining line end shortening data of the test pattern, and establishing a line end shortening rule table; determining an initial correction value according to the line end shortening rule table; and correcting the target pattern according to the initial correction value and the optical proximity effect correction model.

Abstract: Embodiments provide a semiconductor device and a method of manufacturing the same. The method includes: providing a layer to be etched; forming a patterned first mask layer on the layer to be etched; and forming a patterned second mask layer formed on the layer to be etched, where the second mask layer and the first mask layer jointly define an opening, which exposes the layer to be etched; and etching the layer to be etched using the first mask layer and the second mask layer as masks, thus forming a pattern to be etched. The above-described method of manufacturing the semiconductor device allows the feature size of the first mask layer and the second mask layer to be relatively larger while keeping the device feature size the same, makes it possible to further reduce the feature size of the device.

Abstract: A semiconductor structure has a first area, a second area and a third area. The second area is arranged between the first area and the third area. The semiconductor structure includes: a substrate; a shallow trench isolation structure arranged in the substrate and configured to isolate the substrate into a plurality of active areas, in which the active areas in the first area form a semiconductor device; a dielectric layer arranged on the substrate; a through hole structure arranged in the third area and penetrating through the dielectric layer and the substrate; and a stress buffer structure arranged in the second area and including a first buffer doped area, in which the first buffer doped area is arranged in the active areas and formed by doping the active areas with a first buffer impurity.

Abstract: Embodiments provide a method for packaging a semiconductor, a semiconductor package structure, and a package. The packaging method includes: providing a substrate wafer having a first surface and a second surface arranged opposite to each other, the first surface having a plurality of grooves, a plurality of electrically conductive pillars being provided at a bottom of the groove, and the electrically conductive pillar penetrating through the bottom of the groove to the second surface; providing a plurality of semiconductor die stacks; placing the semiconductor die stack in the groove; and filling an insulating dielectric in a gap between a sidewall of the groove and the semiconductor die stack to form an insulating dielectric layer covering an upper surface of the semiconductor die stack to seal up the semiconductor die stack so as to form the semiconductor package structure.

Abstract: A storage system includes: a memory, configured to write or read a plurality of pieces of data during a read-write operation, the plurality of pieces of data being divided into M bytes, and each byte having N pieces of data; and an encoding circuit, configured to in the encoding stage, generate X first check codes based on the two or more pieces of data in each byte, generate Y second check codes based on all data of two or more bytes of the M bytes in the encoding stage, and generate a third check code based on the plurality of pieces of data, the X first check codes and the Y second check codes. The first check codes, the second check codes and the third check code are used to determine an error state of the plurality of pieces of data.

Abstract: The present application relates to a test circuit, comprising: M test units, each test unit having a first terminal and a second terminal, a first terminal of each test unit being connected to a power wire, a second terminal of each test unit being connected to a ground wire, M being a positive integer; each test unit comprises a TDDB test component, a switch, and a control circuit; the TDDB test component has a first equivalent resistance before being broken down, the TDDB test component has a second equivalent resistance after being broken down, and the first equivalent resistance is greater than the second equivalent resistance.

Abstract: The present application relates to the technical field of semiconductor manufacturing equipment, and provides a dust collection device. The dust collection device includes: an air inlet channel, a dust settling channel extending along a preset path, an airflow rotation channel surrounding the settling channel, an air outlet channel and a collection chamber, where one end of the airflow rotation channel is communicated with the dust settling channel, and the other end of the airflow rotation channel is communicated with the air outlet channel; an upstream end of the dust settling channel is communicated with the air inlet channel, and a downstream end of the dust settling channel is communicated with the collection chamber; and the height of the dust settling channel gradually decreases in an extension direction of the preset path.

Abstract: In a bit line lead-out structure preparation method, a bit line extending in a Y-axis direction is formed on a substrate. A contact via covering the bit line in an X-axis direction is formed, the X-axis direction being perpendicular to the Y-axis direction. A metal wire covering the contact via is formed, the contact via being located between the bit line and the metal wire and being in contact with the bit line and the metal wire respectively, wherein a contact area between the contact via and the metal wire is larger than a contact area between the contact via and the bit line.

Abstract: A semiconductor structure includes a substrate and a medium layer located on a first face of the substrate, the substrate has a plurality of first metal layers therein, the medium layer has a magnetic core therein, an orthographic projection of the magnetic core on the first face has a closed ring pattern, the first metal layer has a first end and a second end opposite to each other, an orthographic projection of the first end on the first face is located within a region surrounded by the closed ring pattern.

Abstract: Provided are a data presentation system, method and device, and a computer-readable storage medium. The data presentation system includes: a data collection device configured to collect multiple service system data each from a respective data source and store the service system data in a database; a data parsing device configured to obtain the multiple service system data from the database, and parse each service system data through a respective data model to obtain a data block corresponding to the respective data source; a request responding device configured to: in response to a data request sent by a client, obtain the data block matching the data request as a demanded data block; and a data sending device configured to send the demanded data block to the client to enable a display interface of the client to display the demanded data block.

Abstract: A method for manufacturing a memory includes the following operations. A substrate and a plurality of separate initial bit line contact structures are provided, in which a plurality of active regions are formed in the substrate, and each of the initial bit line contact structures is electrically connected with the active regions, and each of the initial bit line contact structures is partially located in the substrate. Pseudo-bit line structures on the tops of the initial bit line contact structures are formed. The initial bit line contact structures are etched to form bit line contact layers and gaps between the substrate and the side walls of the bit line contact layers. First dielectric layers are formed on the side walls of the pseudo-bit line structures, in which the first dielectric layers are also located right above the gaps.

Abstract: A semiconductor structure and a method for forming the same are provided. The method for forming a semiconductor structure includes the following operations. A substrate is provided. A dielectric layer having a first trench is formed on the substrate. A first filling layer is formed for partially filling the first trench. A first mask layer having a first opening is formed on the dielectric layer. The first opening exposes the first filling layer and part of the dielectric layer. The dielectric is etched by taking the first mask layer as a mask to form a second trench. The first filling layer is removed. And, conductive materials are formed in the first trench and the second trench.

Abstract: A measurement device and method for a semiconductor structure are provided. The measurement device for the semiconductor structure includes a bearing platform, a clamping mechanism, and an image acquisition system. The clamping mechanism is installed on the bearing platform and includes a clamp disposed along a vertical direction. The clamp is configured to clamp the semiconductor structure such that the semiconductor structure is clamped with a to-be-measured surface facing a side. The image acquisition system is disposed by a side of the clamping mechanism, and is configured to acquire a three-dimensional morphology of the semiconductor structure from the side.