Abstract: A sense amplifier (SA), a memory and a control method are provided. The SA includes an amplifying module, configured to amplify voltage difference between a BL and a BLB when the SA is in an amplifying stage; a controllable power module, connected to the amplifying module and configured to stop providing power to the amplifying module when the SA is in a writing stage, to enable the amplifying module to stop working; and a writing module, connected to the BL and the BLB and configured to pull the voltage difference between the BL and the BLB according to data to be written when the SA is in the writing stage. The solution may ensure the successful data writing in a storage unit in a case that a writing circuit has weak drive capability.

Abstract: Provided are a test circuit, a test device and a test method thereof. The test circuit includes: a signal processing module configured to receive a pulse signal to be tested and output a processing signal under a control signal; a sampling module connected to the output terminal of signal processing module and configured to receive the processing signal and generate a sampling signal according to the processing signal. The sampling signal includes a first sampling pulse and a second sampling pulse, the first sampling pulse and the second sampling pulse have a pulse width difference, the pulse width difference is equal to the pulse width of the pulse signal.

Abstract: The present disclosure provides a processing method for semiconductor surface defects and a preparation method for semiconductor devices. The processing method for semiconductor surface defects includes: placing a semiconductor device in a plasma processing device, the semiconductor device comprising a semiconductor substrate and deposition layers formed on the surface of the semiconductor substrate, bubbles being formed in the deposition layers; and plasma bombarding the surface of the deposition layer to break the bubbles, so that the surface of the deposition layer is flat.

Abstract: A manufacturing method for capacitor structure includes: forming a dielectric layer on a first electrode, wherein the dielectric layer includes metal oxide layers doped with preset oxides, and part of the preset oxide and a metal oxide share oxygen atoms; and forming a second electrode on the dielectric layer, wherein the first electrode, the dielectric layer and the second electrode constitute a capacitor structure.

Abstract: A cleaning system is integrated in an exposure machine including an immersion cover and a workbench arranged to be movable in translation below immersion cover. The cleaning system includes an image acquisition component, a cleaning component, and a controller. The image acquisition component is configured to acquire image information of a through hole of immersion cover. The cleaning component includes a cleaning pipe disposed inside workbench and having a first end extending out of a top surface of workbench, and a vacuum pump connected to a second end of cleaning pipe. The controller is configured to judge whether through hole is blocked according to image information, control workbench to be moved in translation so that first end of cleaning pipe is located directly below blocked through hole, and control vacuum pump to apply a negative pressure to blocked through hole through cleaning pipe to clean immersion cover.

Abstract: The present application relates to a chip test method and apparatus, a computer device, and a readable storage medium thereof. The chip test method includes: applying a test signal to a to-be-tested chip; and sending a data signal to the to-be-tested chip such that the to-be-tested chip enters a test mode based on the test signal and the data signal, and regulating a test voltage of the to-be-tested chip.

Abstract: An amplification control method and circuit, a sensitive amplifier and a semiconductor memory are provided. The method includes that: a preset instruction is received, and an isolation power value and a control instruction signal are determined according to the preset instruction; an isolation control signal is generated according to the isolation power value and the control instruction signal; and an amplification circuit receives the isolation control signal and a target signal to be processed according to the preset instruction, and processes the signal to be processed and completes the preset instruction.

Abstract: Provided is an electrostatic discharge protection device, including: a darlington structure formed in a substrate, and a diode string formed in the substrate and including a plurality of diodes connected in series. A first end of the darlington structure is connected to a first voltage, and a second end of the darlington structure is connected to a second voltage. An anode of the diode string is connected to a third end of the darlington structure. A cathode of the diode string is connected to the second voltage.

Abstract: A preparation method of the semiconductor structure includes: providing a substrate including a core device region and an anti-fuse device region; forming a first dielectric layer covering the core device region and the anti-fuse device region; forming a second dielectric layer covering the first dielectric layer and having a dielectric constant larger than a dielectric constant of the first dielectric layer; removing the second dielectric layer on the anti-fuse device region; and forming a conductive layer covering the first dielectric layer on the anti-fuse device region and the second dielectric layer on the core device region.

Abstract: A cleanup system for the semiconductor storage shelf is provided. A semiconductor storage shelf is provided with a plurality of stalls. The cleanup system for the semiconductor storage shelf includes a conveying device and a cleanup device. The cleanup device is configured to clean up each stall of the semiconductor storage shelf. The cleanup device is detachably connected to the conveying device. The conveying device is configured to convey the cleanup device to each stall of the semiconductor storage shelf.

Abstract: Embodiments of the present application provide a semiconductor structure that comprises a semiconductor substrate having a first surface and a second surface opposite to the first surface, a solder pad located at the first surface, a heat transfer layer located at the first surface and being in contact with the solder pad, and a groove located in the semiconductor substrate and being connected to the heat transfer layer.

Abstract: The present application provides a magnetic memory and a reading/writing method thereof. The magnetic memory includes at least one cell layer, the cell layer including: a plurality of paralleled first conductors located in a first plane; a plurality of paralleled second conductors located in a second plane, the first plane being parallel to the second plane, a projection of the second conductor on the first plane intersecting with the first conductor; a plurality of memory elements arranged between the first plane and the second plane, the memory element including a magnetic tunnel junction and a bidirectional gating device arranged in series along a direction perpendicular to the first plane, the magnetic tunnel junction being connected to the first conductor, the bidirectional gating device being connected to the second conductor, and the bidirectional gating device being configured to be turned on when a threshold voltage and/or a threshold current are/is applied.

Abstract: A clock circuit and a memory are provided. The clock circuit includes a data strobe clock circuit and a system clock circuit. The data strobe clock circuit is configured to receive and transmit a data strobe clock signal, the data strobe clock signal is used for controlling at least one of receiving or sending of a data signal. The system clock circuit is configured to receive and transmit a system clock signal, the system clock signal is used for controlling receiving of a command signal. The system clock circuit includes at least two first signal transmission paths, and is configured to transmit the system clock signal via different first signal transmission paths in the at least two first signal transmission paths based on at least one of: different receiving rates, or different sending rates of the data signal.

Abstract: A wafer sample analysis method includes: providing a wafer sample, the wafer sample at least including a slope configured to expose a substrate, a first protective layer and a first doped layer on a same surface, the first protective layer being formed on the substrate, and the first doped layer being formed on the first protective layer; and acquiring and analyzing a slope image of the slope to obtain a doping depth and a doping concentration of elements in the wafer sample in the slope image.

Abstract: The present disclosure relates to the technical field of semiconductor packaging, and discloses a semiconductor structure and a method for forming the same. The method includes: providing a chip, the chip having interconnect structures on its surface, the top of the interconnect structures having an exposed fusible portion; providing a substrate, the substrate having conductive structures on its surface; patterning the conductive structures so that edges of the conductive structures have protrusions; combining the chip with the substrate.

Abstract: The present disclosure provides a sense amplification structure and a memory architecture. The sense amplification structure includes: a first PMOS transistor provided with a gate connected to a second readout bit line and a source connected to a first signal terminal; a first NMOS transistor provided with a gate connected to an initial bit line; a drain of the first PMOS transistor and a drain of the first NMOS transistor being connected to a first complementary readout bit line; a second PMOS transistor provided with a gate connected to the second complementary readout bit line; a second NMOS transistor provided with a gate connected to an initial complementary bit line and a source connected to a second signal terminal; a drain of the second PMOS transistor and a drain of the second NMOS transistor being connected to the first readout bit line.

Abstract: A column select signal cell circuit, a bit line sense circuit and a memory are disclosed. The column select signal cell circuit includes four column select cells, each of which includes 4*N input and output ports, 4*N bit line connection ports and one control port. The control ports of a first column select cell and a fourth column select cell are connected to a first column select signal, and the control ports of a second column select cell and a third column select cell are connected to a second column select signal. The bit line connection ports of the first column select cell and the third column select cell are connected to 8*N bit lines of a first storage unit group, the bit line connection ports of the second column select cell and the fourth column select cell are connected to 8*N bit lines of a second storage unit group.

Abstract: Embodiments relate to a method for fabricating a semiconductor structure, a semiconductor structure, and a peripheral circuit. The method for fabricating a semiconductor structure includes: providing a substrate; forming a gate initial structure and a residue on the substrate; and removing the residue by means of a first cleaning liquid. The first cleaning liquid is capable of inhibiting the residue from undergoing a hydrolysis reaction.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure, relating to the technical field of semiconductors. The method of manufacturing a semiconductor structure includes: providing a substrate; forming active pillars arranged in an array on the substrate, a projection shape of a longitudinal section of each of the active pillars includes a cross shape; forming a first oxide layer on the substrate, where a filling region is formed between adjacent active pillars in the same row; sequentially forming a word line and a dielectric layer in the filling region; exposing a top surface of each of the active pillars; forming a contact layer on the active pillars; and forming a capacitor structure on the contact layer.

Abstract: The present disclosure relates to a semiconductor device and a preparation method thereof. The method for preparing a semiconductor device comprises: providing a first dielectric layer; forming a first window in the first dielectric layer; forming a first connection structure in the first window; forming a second dielectric layer on the first dielectric layer, the second dielectric layer having a second window from which at least the first connection structure is exposed; forming a first barrier layer on the sidewall and bottom of the second window, the first barrier layer comprising an opening from which part of the first connection structure is exposed; and forming a second connection structure in the second window.