Abstract: A manufacturing method for memory includes providing a substrate; forming a first isolation layer on the substrate; forming a first mask layer on the first isolation layer; forming a second isolation layer on the first mask layer and part of the first isolation layer; forming a second mask layer on the second isolation layer; removing part of the second mask layer and part of the second isolation layer; removing the first mask layer and the remaining second mask layer; forming a third mask layer on the first isolation layer and the remaining second isolation layer; removing part of the third mask layer; and etching the remaining part of the second isolation layer and the first isolation layer below the second isolation layer, by taking the remaining third mask layer as a mask.

Abstract: An image view angle conversion method includes: model training data are obtained, the model training data including planar images of a training object at a plurality of different view angles and labels corresponding to respective view angles, where the labels corresponding to the different view angles are different. A pre-designed generative adversarial network model is trained according to the model training data to obtain a view angle conversion network model. A planar image of a target object and labels corresponding to one or more expected view angles of the target object are input into the view angle conversion network model, so that the view angle conversion network model generates planar images of the target object at the expected view angles.

Abstract: An embodiment of the present application provides a test method for tolerance against the hot carrier effect, applied to an I/O circuit of a memory, the I/O circuit having an output terminal, comprising: controlling the output terminal to alternately output a first level and a second level, the first level being higher than the second level; obtaining a degradation rate of an output performance parameter of the I/O circuit according to the first level and the second level; and obtaining tolerance of the I/O circuit against the hot carrier effect based on the degradation rate.

Abstract: A method for preparing a semiconductor device includes: providing a semiconductor substrate, in which a trench is formed on the semiconductor substrate, a filling layer is formed in the trench, and a void is formed in the filling layer; removing a portion of the filling layer to expose the void; forming a plug, in which the plug is configured to plug the void and extends into the void by at least a preset distance; and removing a portion of the filling layer and remaining the plug with at least a preset height until the filling layer reaches a preset thickness to form a contact hole.

Abstract: A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The method for manufacturing the semiconductor structure includes: providing a substrate, in which the substrate includes an array area and a peripheral area adjacent to each other, and the array area includes a buffer area connected to the peripheral area; forming a first dielectric layer, a first supporting layer, a second dielectric layer, a second supporting layer and a third dielectric layer, which are successively stacked onto one another, on the substrate, forming a groove-type lower electrode, which at least penetrates through the third dielectric layer and the second supporting layer, in the buffer area; removing the third dielectric layer through a wet etching process; and etching the second supporting layer in the peripheral area after removing the third dielectric layer.

Abstract: A semiconductor device manufacturing method includes: providing a semiconductor base; patterning the first medium layer to form a groove extending along the base in the base; forming a first auxiliary layer and a first metal layer sequentially in the groove, where the first metal layer is located on the side of the first auxiliary layer towards the first medium layer; thinning the base on the second surface of the base to expose the first auxiliary layer; removing the first auxiliary layer to form a first opening; and forming a second metal layer on the second surface of the base, where the second metal layer fills the first opening.

Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate; a transistor, including a control terminal, a first terminal, and a second terminal; a first magnetic memory structure, a bottom electrode of which is electrically connected to the first terminal of the transistor; a second magnetic memory structure, a top electrode of which is electrically connected to the first terminal of the transistor, the bottom electrode of the first magnetic memory structure is located in a same layer with a bottom electrode of the second magnetic memory structure; a first bit line, electrically connected to a top electrode of the first magnetic memory structure; a second bit line, electrically connected to the bottom electrode of the second magnetic memory structure; and a selection line, electrically connected to a second terminal of the transistor.

Abstract: A testing circuit includes: a first sampling module configured to receive a to-be-tested pulse signal, and generate a first sampled signal according to the pulse signal; and a second sampling module configured to receive the pulse signal, and generate a second sampled signal according to the pulse signal. The second sampled signal and the first sampled signal have a phase difference, the phase difference being equal to a pulse width of the pulse signal.

Abstract: A memory includes a substrate, a control circuit layer located in the substrate, and at least two memory structure layers. The control circuit layer includes at least part of control circuits of the memory. The at least two memory structure layers are sequentially stacked on the control circuit layer. Each memory structure layer includes multiple memory blocks arranged in an array. The memory block includes multiple parallel Word Lines (WLs) extending in a first direction. The first direction is parallel to a surface of the substrate. An opening is provided between adjacent memory blocks located in the same memory structure layer. The openings located in different memory structure layers go through each other. WLs in the at least one memory structure layer are connected to the control circuit layer through the openings that go through each other.

Abstract: A semiconductor structure includes: a high-speed circuit module including a clock signal with a frequency greater than a first threshold; a first conductive metal layer including power conductive wires extending along a first direction and arranged at intervals, and the power conductive wires being electrically connected with the high-speed circuit module; and a redistribution layer located above the first conductive metal layer and including power pads and electrical wires connected with the power pads, in which the power pads are located at one side of the high-speed circuit module, a projection of the power pads does not overlap with that of the high-speed circuit module, the electrical wires include a first electrical wire region where the electrical wires are repeatedly bent, the first electrical wire region at least partially covers the high-speed circuit module, and the electrical wires are used for electrically connecting the power conductive wires and power pads.

Abstract: The application provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a substrate and multiple Word Lines (WLs), the multiple WLs extend along a first direction and are arranged on the substrate at intervals along a second direction, a WL isolation structure is arranged between every two adjacent WLs and includes at least a first isolation layer and a second isolation layer stacked along the second direction and made of different materials, and the first direction and the second direction intersect with each other.

Abstract: A method for manufacturing a semiconductor structure and the semiconductor structure are provided. The method includes the following operations. A substrate provided with a plurality of active areas arranged at intervals is provided. A first laminated structure and a first photoresist layer are sequentially formed on the substrate. Negative Type Develop (NTD) is performed on the first photoresist layer, to form a first pattern. The first laminated structure is etched along the first pattern, to form a second pattern in the first laminated structure. The substrate is etched up to a preset depth by taking the first laminated structure having the second pattern as a mask, to form a recess and form a plurality of protuberances arranged at intervals on the reserved substrate. The recess surrounds the protuberance, and the active area is exposed between the protuberances.

Abstract: An embodiment of the present disclosure provides a method of manufacturing a semiconductor structure. The method includes: providing a base; and forming a silicon nitride film layer on the base by an atomic layer deposition process, where the atomic layer deposition process includes multiple cyclic deposition steps; in each of the cyclic deposition steps, a silicon source gas and a nitrogen source gas are provided to a surface of the base; before each of the cyclic deposition steps, the method of manufacturing a semiconductor structure further includes a repair step; in the repair step, a repair gas is provided to the surface of the base, and the repair gas is a hydrogen-containing repair gas; the repair gas includes a polar molecule for repairing the surface of the base that is damaged.

Abstract: A memory includes: a memory cell array; a first column decoder, coupled to the memory cell array and configured to perform a write operation on the memory cell array; a second column decoder, coupled to the memory cell array and configured to perform a read operation on the memory cell array; and a read amplifier, the read amplifier and the second column decoder being located on two opposite sides of the memory cell array, the read amplifier being coupled to the memory cell array and configured to receive read data information output by the memory cell array based on the read operation. The read amplifier, the first column decoder, the memory cell array and the second column decoder are arranged in a first direction, and the first column decoder and the second column decoder are located on two opposite sides of the memory cell array.

Abstract: A semiconductor structure, a method for preparing the semiconductor structure and a memory are provided. The method includes: providing a wafer in which multiple conductive pillars are formed; inverting the wafer and performing etching on a back plane of the wafer to expose each conductive pillar from the back plane of the wafer, and lengths of the multiple conductive pillars exposed to the back plane are different; depositing an insulation layer on the back plane of the wafer and the conductive pillars, and depositing a filling layer on the insulation layer, the filling layer completely covering back ends of the multiple conductive pillars; and performing polishing on the filling layer and back ends of a part of the conductive pillars, until a back end of each conductive pillar is exposed and the back ends of the multiple conductive pillars are flush with a back plane of the filling layer.

Abstract: A semiconductor structure includes a plurality of dies. The plurality of dies are stacked sequentially along a first direction. The first direction is a direction perpendicular to a plane of the dies. Each of the dies includes a base and n first conductive structures penetrating the base along the first direction, where n is greater than or equal to 2. In at least one group of the corresponding first conductive structures in the dies, projections of the group of the first conductive structures in two adjacent layers of the dies along the first direction are not overlapped with each other.

Abstract: A memory includes: a storage cell array; a write driver; and a first column decoder, the first column selection line includes a dummy route and a loaded route, the dummy route is coupled to the first column decoder and the loaded route and transmits a first column selection signal to the loaded route; the loaded route is coupled to a first storage cell area and transmits the first column selection signal to the first storage cell area; the first column selection signal selects a storage cell column, on which a write operation is performed, from the first storage cell area. A transmission direction of a data signal to be written transmitted by the write driver is identical to a transmission direction of the first column selection signal transmitted via the loaded route.

Abstract: A semiconductor structure includes: multiple active areas arranged in an array along intersecting first and second directions and spaced apart by an isolation structure; a bit line select structure comprising a first gate, a second gate, a third gate and a fourth gate located on four mutually adjacent active areas, and at least one connecting line located on the isolation structure; and multiple contact structures, each of the multiple contact structures being located on one side, close to the connecting line, of both sides of a respective gate and connected with a respective one of the multiple active areas, and an orthographic projection of the contact structure on a plane where the active area is located being at a position, close to the connecting line, in the active area.

Abstract: A transistor includes a source structure, a trench, a drain structure, and a gate structure. The trench sequentially has first and second end faces which are arranged opposite in a first direction. The source structure extends from the first end face in a second direction. The source structure sequentially has third and fourth end faces which are arranged opposite in the first direction. The fourth end face is connected to the first end face. The drain structure extends from the second end face in a direction opposite to the second direction. The drain structure sequentially has fifth and sixth end faces which are arranged opposite in the first direction. The fifth end face is connected to the second end face. The second direction intersects the first direction. The gate structure surrounds the trench and is connected to the fourth and the fifth end face.

Abstract: A method for manufacturing a semiconductor structure includes: providing a substrate including a transistor structure; forming a laminated structure on the substrate, the laminated structure including a dielectric layer and an insulating layer which are sequentially stacked in a thickness direction of the substrate, and the insulating layer being arranged on a side, away from the substrate, of the dielectric layer; forming a through hole penetrating through the laminated structure in the laminated structure to expose a source/drain of the transistor structure; and etching at least part of a side wall of the through hole located in the dielectric layer to form a conductive hole in the insulating layer and the dielectric layer. An aperture size of a medial part of the conductive hole is greater than an aperture size of each of both ends of the conductive hole.