Abstract: A method for simulating a placement of patterns by self-assembly of block copolymers in a contour printed on a plate by lithography includes: extraction of geometric parameters of the contour recorded in a memory; selection, by a processor having access to the memory, of at least one local extremum of an interference figure produced inside the contour on the basis of the geometric parameters of the contour by applying a model for propagation of waves interfering with one another; and provision, by the processor and on the basis of the local extremum, of parameters for placement of at least one pattern intended to be obtained by self-assembly of block copolymers within the contour.

Abstract: The invention relates to a method for recording a source image, in which a reproduction of the source image is made in the form of a matrix of elementary patterns. The method comprises the following steps: deposition (401) of a first opaque layer (42) on a first substrate (41); etching (402) of the first opaque layer (42) so as to form a matrix of first cells (440) each having one from amongst several first predetermined patterns; deposition of at least one second opaque layer (45); and etching of the second opaque layer (45), so as to form a matrix of second cells (470) each having one from amongst several second pre-determined patterns, the elementary patterns being defined by the superimposition of a second pattern and a first pattern. The invention also relates to an image medium obtained by means of such a method.

Abstract: The invention concerns a method for producing a transistor. The gate of the transistor is produced after having produced source and drain electrodes of the transistor. From a substrate having a stack of layers comprising at least two surface layers with a first layer of a first semiconductor material intended to produce a conduction channel of the transistor, and a second layer of a second semiconductor material situated on the first layer and intended to at least partly produce the source and drain electrodes of the transistor, the formation of a mask defining a cavity of a gate pattern and the creation of lateral recesses at the periphery of the gate pattern in the second layer and under the mask by an isotropic etching of the second material, and in that it comprises a filling of the lateral recesses with a dielectric material so as to form gate spacers therein.

Abstract: The invention relates to a device for converting heat energy into mechanical energy comprising a first (4) and a second (6) bistable area passing from a first stable state to a second stable state by means of a thermal effect or mechanical action, said areas (4, 6) being mechanically coupled such that the passage from one state to the other of one area (4, 6) by means of a thermal effect causes the other area (6,4) to pass from one state to the other, each area (4, 6) having a blistering temperature and an unblistering temperature, the blistering temperature being higher than the unblistering temperature. Said device is intended to be placed in contact with an environment (SC) having at least one given temperature, such that the temperature of the environment (SC) is lower than the blistering temperature of the first area (4) and is higher than the blistering temperature (Tc6) of the second area (6).

Abstract: The invention more particularly relates to a resistive memory cell comprising a first and a second metal electrodes and a solid electrolyte positioned between the first and the second metal electrodes, with the solid electrolyte comprising a commutation layer in contact with the first electrode and a dielectric layer, with said resistive memory cell being able to be electrically modified so as to switch from a first resistive state to a second resistive state (state LRS) wherein the resistance (RON) of the memory cell is at least ten times smaller than the resistance (ROFF) of the memory cell in the HRS state, in the LRS state the first electrode being so arranged as to supply metal ions intended to form at least a conductive filament through said commutation layer, with the cell being characterised in that, in the LRS state, the memory cell is conductive for a range of voltages between 0 Volts and VREST 2 .

Abstract: A device for extraction of at least one analyte contained in a liquid sample, including an extraction and desorption zone of the analyte with a stationary phase as the extraction zone, a liquid supply inlet to the extraction zone, a gas supply inlet to the extraction zone, an evacuation outlet from the extraction zone that will be connected to either a collection tank, or a device for analysis of the analytes, a valve configured to connect the extraction zone to one of the supply inlets, a valve configured to connect the extraction zone to one of the evacuation outlets, a mechanism heating the valve zone such that when the extraction zone is supplied with liquid, evacuation from the extraction zone takes place to the collection tank.

Abstract: A light-emitting device comprising at least: a metal layer able to be heated and to propagate surface waves consecutive to the heating of the metal layer, with the metal layer being structured such that it comprises several diffraction patterns able to carry out a diffraction of the surface waves to free-space propagation modes, and wherein a synthetic hologram is encoded such that a phase image of each pixel of the hologram is encoded by an offset in the position of one of the diffraction patterns; a heater of the metal layer.

Abstract: The invention concerns a filter bank receiver (FBMC) effecting a carrier frequency offset compensation in the frequency domain. The receiver comprises an FFT module extended by the overlap factor (610), a module (630) offsetting a predetermined number of subcarriers at the output of the FFT followed by a filter for reducing interference between subcarriers (640), the number of subcarriers and the coefficients of the interference reduction filter being determined from an estimation () of the frequency offset. The vector of samples thus obtained is then the subject of channel equalisation (650) before being filtered by a battery of analysis filters and spectrally de-spread (660). Finally, after spectral de-spreading, the vector of samples is demodulated by an OQAM demodulation (670) so as to recover the transmitted data.

Abstract: Photodetecting device comprising: a semiconductor layer doped according to a first type of conductivity; two first semiconductor portions doped according to a second type of conductivity opposed to the first type of conductivity, distinct and separated from one another, and arranged in the semiconductor layer next to one another; a second semiconductor portion doped according to the first type of conductivity with a level of doping greater than that of the semiconductor layer and delimiting, with the semiconductor layer, the first portions by forming p-n junctions, wherein a part of the semiconductor layer separates the first portions such that the depletion zones between the first portions form a potential barrier of which the level is less than the potential of the second portion and of the semiconductor layer.

Abstract: The invention relates to a semiconducting structure intended to emit light, comprising a first semiconducting region (10) with a first type of conductivity, and a second semiconducting region (20) with a second type of conductivity, at least on a portion (220, 210), so as to form a junction semiconducting with the first region (10). This second region (20) has at least a first portion (210) in contact with the first region (10), this first portion (210) comprising at least one first and one second carrier confinement zone (211, 212). The structure (1) comprises at least a first means of polarising the first portion (210) adapted to apply direct first external polarisation to the first portion (210) in order to modify the distribution of carriers of at least one type of conductivity in the first portion (210) relative to the first and second confinement zones (211, 212). The invention also relates to a method of manufacturing a semiconducting structure (1) and a device comprising at least such a structure (1).

Abstract: A Method for making a separation between an active zone of a substrate located on its front face from a given portion of the substrate located on its back face, wherein trenches and cavities wider than the trenches are formed to extend said trenches, such that at least one given cavity formed to extend a given trench is adjacent to another cavity, and when the cavities have been filled with a given material, they form a separation zone between said active zone and a given portion of the substrate that will be removed later.

Abstract: A photovoltaic solar module including at least one photovoltaic cell including a first transparent polymer layer surrounding the cell on all or some of its sides and a second transparent polymer layer surrounding the first transparent polymer layer on all or some of its sides. The second transparent polymer layer has a thickness greater than or equal to 0.5 mm and a Shore hardness D greater than that of the first polymer layer.

Abstract: The invention relates to a method for producing a spinel iron oxide layer. textured according to a preferred crystal orientation along the [111] direction, with the spinel iron oxide layer being a ferrite layer or a doped ferrite layer, characterised in that it comprises: producing a bottom layer of titanium (Ti) or titanium oxide (TiOx), with the thickness of the bottom layer being greater than or equal to eight nanometres; producing a spinel iron oxide layer on the bottom layer produced beforehand. It also relates to a device comprising a layer of textured ferrite.

Abstract: Adiabatic logic circuit having a first and a second inputs, a first and a second outputs and at least one supply and synchronisation input (Phi), with this circuit comprising: a first logic device comprising at least one first microelectromechanical and/or nanoelectromechanical switch, referred to as first mechanical switch, controlled by a first input and connected to the first output and to the supply and synchronisation input, a second logic device opposite the first logic device comprising at least one second microelectromechanical or nanoelectromechanical switch, referred to as second mechanical switch, controlled by the second input and connected to the second output and to the supply and synchronisation input, first and second devices for partial discharging connected respectively between the first output and the supply and synchronisation input and between the second output and the supply and synchronisation input.

Abstract: The invention concerns a method for producing a metal coating on a portion of the surface of a substrate of a microelectronic device, wherein it comprises, using a modified nucleic acid strand comprising a nucleic acid strand structure, at least one metal nanoparticle and/or a metal atom and at least one chemical function, at least one step of fixing the chemical function of the at least one modified nucleic acid strand on the portion of the surface of the substrate.

Abstract: A ligand recombinant protein inhibiting HB-EGF (Heparin-Binding Epidermal Growth Factor like), from the R domain of diphtheria toxin, which can be used for the treatment and diagnosis of diseases involving the activation of the HB-EGF/EGFR pathway.

Abstract: A system for managing correspondence between a cache memory, subdivided into a plurality of cache areas, and a main memory, subdivided into a plurality of memory areas, includes: a mechanism allocating, to each area of the main memory, at least one area of the cache memory; a mechanism temporarily assigning, to any data row stored in one of the areas of the main memory, a cache row included only in one cache area allocated to the main memory area wherein the data row is stored; and a mechanism generating and updating settings of the allocation by activating the allocation mechanism, the temporary assigning mechanism configured to determine a cache row to be assigned to a data row based on the allocation settings.

Abstract: A method for depositing particles on a substrate, or a running substrate, including: (a) producing at least one first compact film of particles floating on a carrier liquid provided in a transfer area having an outlet of particles arranged facing the substrate; (b) producing at least one pattern by depositing a substance on the first film in the transfer area, along a contour of the pattern, the substance maintaining the particles of the film together in contact with the substance; (c) removing at least one portion of the particles of the first film located interiorly relatively to the contour, or exteriorly relatively to the contour; and then (d) transferring patterns onto the substrate through the outlet of particles.

Abstract: A method for evaluating sealing of a bipolar structure including a sheet-like substrate forming a current collector, and two electrodes in a form of films arranged on opposite surfaces of the substrate, respectively, the method including: placing the bipolar structure in a cavity to define first and second compartments therein, which are separated by the bipolar structure, a periphery of which is sealingly connected to the cavity; circulating a fluid in the first compartment of the cavity toward the second compartment; and evaluating sealing of the bipolar structure from a measurement of difference in pressure of the fluid in the first and second compartments.

Abstract: Method for fabricating a transistor comprising the steps consisting of: forming sacrificial zones in a semi-conductor layer, either side of a transistor channel zone, forming insulating spacers on said sacrificial zones against the sides of the gate of said transistor, removing said sacrificial zones so as to form cavities, with the cavities extending on either side of said channel zone and penetrating under said spacers, forming doped semi-conductor material in said cavities, with said semi-conductor material penetrating under said spacers.