Abstract: A method, apparatus and computer system for detecting the insertion of a medium in a medium drive, including applying energy to a drive motor of the medium drive; changing the state of a medium change signal, in response to the energy, to reflect the presence of a medium in the medium drive; and relaxing the energy before the drive motor turns.

Abstract: A power distribution system, for use in computer systems and switchable to distribute uninterruptable power received from either of a first or a second power supply, includes a first and a second power input receptacle each being connected to the first and second power supplies respectively. A switch is connected to both the first and the second power input receptacles and is for switching between power received at the first power input receptacle from the first power supply and power received at the second input power receptacle from the second power supply. Two outputs, each with multiple outlet connectors, are connected to the switch and are used for distributing and outputting the power received from either of the first or second power supplies.

Abstract: A device for enabling and disabling the supply of power from a power source to a computer, the power source having a primary side and a secondary side, the device including an interlock switch connected to the computer, the interlock switch selectably positionable between open and closed positions; and two optocouplers coupled in parallel, both of which are referenced to the secondary side of the power source. When the interlock switch is closed, the first optocoupler is active. This enables the supply of power from the power source to the computer. When the interlock switch opens, the first optocoupler shuts off. This disables the supply of power from the power source to the computer. Further when the interlock switch is opened, the second optocoupler is saturated. This overrides the regulation feedback circuitry from regulating the power supplied by the power source driving the power outputted to the computer to zero. When the interlock switch is closed, the second optocoupler operates in the linear region.

Abstract: A TV/PC convergence device, operable in a television mode, a computer mode and a combination television/computer mode, includes a display, a computer and a tracking device. The display receives and displays images in all three modes. The computer executes programs and is operable in the computer mode and the combination television/computer mode. The tracking device, which is coupled to the display and computer, tracks, records, and reports select uses of the display and the computer during each of the television mode, the computer mode and the combination television/computer mode.

Abstract: A processing system includes a cache memory system which receives an address and a memory request from a processor. Simultaneously, information is accessed responsive to the address from a main memory and from a cache memory. During access of the information from the main memory and cache memory, it is determined whether the desired information is stored in the cache memory. If so, the information is output from the cache memory; if not, the information is output from the main memory.

Abstract: Burst SRAMs designed for operation at a given data rate corresponding to the frequency of a first clock signal but capable of operation using a higher frequency clock signal. The burst SRAMs are preferably incorporated into the cache memory of a second level cache coupled to the processor bus in a computer system, where the computer system is preferably based on a 66-MHz P5 microprocessor. A cache controller, preferably incorporated within a memory controller, controls operation of the second level cache memory by providing the address load and address advance signals. The burst SRAMs are capable of recognizing the faster clock pulses, as well as the shorter pulses asserted on the address load and address advance signals. The address control signals are asserted and then negated during consecutive clock cycles of the faster clock signal, so that the burst SRAMs effectively operate at the same data rate corresponding to the lower frequency clock signal.

Abstract: A hub circuit with an integrated bridge circuit carried out in software including a switch for bypassing the bridge process such that the two bridged networks effectively become one network. An in-band management process in software is disclosed which receives and executes network management commands received as data packets from the LANs coupled to the integrated hub/bridge. Also, hardware and software to implement an isolate mode where data packets which would ordinarily be transferred by the bridge process are not transferred except in-band management packets are transferred to the in-band management process regardless of which network from which they arrived. Also disclosed, a packet switching machine having shared high-speed memory with multiple ports, one port coupled to a plurality of LAN controller chips coupled to individual LAN segments and an Ethernet microprocessor that sets up and manages a receive buffer for storing received packets and transferring pointers thereto to a main processor.

Abstract: A speaker system for use in a thin film video monitor apparatus is disclosed. The video monitor apparatus includes a thin film video display panel as well as a stiffening panel adjacent to the thin film video display panel. Next, a plurality of piezo speaker transducers are attached to one of the sides of the stiffening panel. The stiffening panel typically is composed of a material such as aluminum honeycomb sheets or a polycarbonate sheet. Other materials for use as the stiffener may include magnesium shells or ABS plastic. The speakers are defined so that a first sound channel and a second sound channel are provided, and these sound channels can define a left and right channel for proper stereo imaging. Between the video monitor and the stiffening panel is located an electromagnetic interference (EMI) shield.

Abstract: A computer system includes a chassis having a generally planar floor plate; a first generally planar motherboard having circuitry thereon mounted on the floor plate; at least one riser board connected to the first motherboard to extend generally orthogonally upwardly therefrom, the riser board having an upper edge oriented generally parallel to and above the plane of the first motherboard, and being provided with electrical circuit contacts along the upper edge; and a second generally planar motherboard connected to and at least partly supported by the riser board, the second motherboard being positioned adjacent the upper edge of the riser board, the second motherboard having circuitry thereon electrically connected to the electrical circuit contacts along the upper edge of the riser board.

Abstract: An assembly for facilitating the installation, securement and removal of a computer component from a computer chassis. The assembly includes a base connectable to the computer chassis and a handle pivotally connected to the base. The handle includes a notch and tab portion at each end for engaging a portion of the computer chassis for facilitating the installation of the component with the computer chassis when the handle is pivoted in a first direction and for facilitating the removal of the component from within the computer chassis when the handle is pivoted in a second direction. The handle further includes an aperture for receiving a flexible interlock tab connected to the base for releasable interlocking the handle and the base together, such that this, along with the tab portions of the handle, facilitate securing the computer component within the computer chassis.

Abstract: A hub circuit with an integrated bridge circuit carried out in software including a switch for bypassing the bridge process such that the two bridged networks effectively become one network. An in-band management process in software is disclosed which receives and executes network management commands received as data packets from the LANs coupled to the integrated hub/bridge. Also, hardware and software to implement an isolate mode where data packets which would ordinarily be transferred by the bridge process are not transferred except in-band management packets are transferred to the in-band management process regardless of which network from which they arrived. Also disclosed, a packet switching machine having shared high-speed memory with multiple ports, one port coupled to a plurality of LAN controller chips coupled to individual LAN segments and an Ethernet microprocessor that sets up and manages a receive buffer for storing received packets and transferring pointers thereto to a main processor.

Abstract: A method and apparatus for increasing system functionality through a predefined interface is disclosed. Signal lines which are not used or which are not used in certain modes are connected to an interconnection device instead of being connected to an interface wherein the output of the interconnection device is connected to the interface where such lines would have been connected. The interconnection device also has a set of inputs for receiving signals from a device providing the desired functionality. A controller chooses between the two sets of inputs to control what signal lines are connected to the predefined interface. Accordingly, during certain modes of operation, the added functionality from a device whose output is being switched into the interface can be supported. In one embodiment, speaker phone capability is provided for even though the predefined PCMCIA interface does not support such capability.

Abstract: A card guide assembly for isolating printed circuit boards from each other during insertion and removal from a mounting array. The assembly includes first and second isolation channels that are configured to permit the receipt of a variety of PC board sizes therein and a securement cap for receipt thereover. The cap may be adjustably positioned within the isolation channels for establishing a secured mounting for a variety of PC board sizes. A locking mechanism is provided between the cap and the channels for secured engagement therebetween. The channels are mounted on opposite sides of the PC board connector region permitting conventional mounting of the PC board into a mounting connector.

Abstract: A computer system capable of booting currently manufacturable CD-ROMs or tapes without altering the ISO standard or requiring special, customized software to perform this function. A CD-ROM developed for booting according to the present invention contains a boot record as defined by the ISO but located at the end of the defined system area. The operating code of the computer scans for a boot record starting at the beginning sector of the CD-ROM and ending at either a default number or the volume descriptor terminator. The floppy disk boot images are contained at the end of the primary volume space and incorporated in the primary volume space, not external to the primary volume space as in the ISO standard. Boot code contained in the boot record determines the size of the volume, and the proper floppy image to be used and then the actual location of the floppy image. Booting of the system then commences using the floppy image.

Abstract: A network (10) includes a repeater (12) that can service data devices that operate using different communications protocols. The data devices (18, 20, 22) couple to the ports (34) of the repeater (12), and operate using a first communications protocol in a first domain (14). The data devices (26, 28, 30) also couple to the ports (34) of the repeater (12) and operate using a second communications protocol in a second domain (16). Information on the operation of a port (34) may be displayed using one port indicator (202) or two port indicators (300, 302).

Abstract: An electronic device includes a host component having a first antenna; and a radio unit that may be connected to the host component and that has a second, rotatable antenna. The radio unit also includes a switch that is triggered by rotation of the second antenna to activate either the first antenna or the second antenna.

Abstract: A n-key rollover keyboard having an application specific integrated circuit (ASIC) with a large number of pins, each pin directly connected to a key contact, with the other side of the key contact connected to ground. The direct wire arrangement allows use of a single sided circuit board. The keyboard has a reduced cost over prior n-key rollover designs by allowing removal of the series diodes and double sided circuit board.

Abstract: Double buffering operations to reduce host bus hold times when an expansion bus master is accessing the main memory on a host bus of a computer system. A system data buffer coupled between the main memory and the expansion bus includes 256-bit double read and write buffers. A memory controller coupled to the double read and write buffers and to the expansion bus includes primary and secondary address latches corresponding to the double buffers. The memory controller detects access to the main memory, compares the expansion bus address with the primary and secondary addresses and controls the double read and write buffers and the primary and secondary address latches accordingly. During write operations, data to be written to the same line of memory is written to a first of the double write buffers until a write occurs to an address to a different line before data is transferred to main memory.

Abstract: A circuit for configuring a Plug and Play expansion card in one of three ways. The first is the standard Plug and Play configuration method, wherein expansion cards go through the isolation process to obtain unique Card Select Numbers (CSN). This method requires the existence of a dedicated serial EEPROM to store the system resource data for the expansion cards. However, when an expansion card is directly mounted onto a system board, it becomes a system board device. This allows the separate serial EEPROM to be removed. To implement, two alternative configuration modes are provided, wherein the expansion card can be configured under main CPU control. In these alternative modes, the configuration data is stored in the main system BIOS ROM. In the first mode, a register in the expansion card is mapped to a fixed ISA I/O address. In the second mode, the register is controlled by a dedicated pin, thus allowing it to be mapped to any ISA I/O address.

Abstract: A battery pack for a computer system including static memory to maintain battery operating parameters and charge information, a real time clock (RTC) for measuring periods of non-use of the battery and a communication circuit to exchange the battery information with a microcontroller located in the computer system. The static memory, RTC and communication circuit is preferably in the form of a single RAM/RTC chip. The battery pack also includes circuitry to maintain power to the RAM/RTC from the battery if AC power is not available. The microcontroller detects the presence of the battery and retrieves the present time from the RTC, a timestamp indicating time or removal of the battery and other operating parameters and charge information from the battery pack, and controls the charging functions of the battery accordingly. The microcontroller also updates the charge information of the battery pack while performing other housekeeping functions of a DC--DC converter.