Abstract: A method and device for reliably assessing the integrity of a computer system's software prevents execution of corrupted programs at time of system initialization, enhancing system security. Programs and data comprising the system's trusted software, including all startup processes, are verified before being utilized. Methods to verify the trusted software use a hierarchy of both modification detection codes and public-key digital signature codes. The top-level codes are placed in a protectable non-volatile storage area, and are used by the startup program to verify the integrity of subsequent programs. A trusted initialization program sets a hardware latch to protect the codes in the non-volatile memory from being overwritten by subsequent untrusted programs. The latch is only reset at system restart, when control returns to the bootstrap program. Software reconfiguration is possible with trusted programs that write new top-level codes while the latch is open.

Abstract: A computer system capable of booting currently manufacturable CD-ROMs or tapes without altering the ISO standard or requiring special, customized software to perform this function. A CD-ROM developed for booting according to the present invention contains a boot record as defined by the ISO but located at the end of the defined system area. The operating code of the computer scans for a boot record starting at the beginning sector of the CD-ROM and ending at either a default number or the volume descriptor terminator. The floppy disk boot images are contained at the end of the primary volume space and incorporated in the primary volume space, not external to the primary volume space as in the ISO standard. Boot code contained in the boot record determines the size of the volume, and the proper floppy image to be used and then the actual location of the floppy image. Booting of the system then commences using the floppy image.

Abstract: A computer system that flushes an internal cache in the microprocessor and an external cache to insure cache coherency. The computer system will flush the caches when a write command is directed to those specific portions that are write protected. The microprocessor is placed in a hold state before the flushing process is initiated. The cache memories are then cleared. Thus the microprocessor will not be able to read the incoherent information stored in the cache and yet data obtained during read operations can be cached for performance increase.

Abstract: A tapped inductor slave regulating circuit provides a second slave output voltage derived from a tapped connection to the filter storage inductor of a first output voltage of a switching power supply converter. In the converter, an unregulated voltage is provided through a switching circuit to a storage inductor to develop a first output. The switching circuit is turned off and a synchronous rectifier is turned on to freewheel the current through the storage inductor and the load. The storage inductor is center-tapped and coupled to a switching circuit to provide a second slaved output. The location of the center tap is chosen to provide the proper voltage of the second output. In one embodiment, the switching circuit for the slaved output is turned on during the freewheel portion of each cycle to provide a proper voltage level for the second output. In another embodiment, a separate local feedback circuit is provided to further regulate the second output voltage level.

Abstract: A synchronous memory controller capable of operating with three different frequency microprocessors and yet providing similar DRAM timings. Input frequencies of 32, 25 and 33 MHz correspond to 16, 25 and 33 MHz microprocessors. Various states are bypassed at certain frequencies to allow the various memory, latch and buffer control signals to be produced uniformly. The memory controller also handles operations from external buses, such as the EISA and ISA buses at the various input frequencies. These external bus cycles are controlled by separate state machines, which also have states bypassed for certain input frequencies.

Abstract: An apparatus for performing Least Recently Used techniques for a four way set associative cache system which includes a random access memory (RAM) which stores the ways representing the least recently used (LRU), most recently used (MRU) and LRU+1. The MRU-1 is developed by XORing the other three LRU way information values. Processor or snoop operation is determined and the way use aging information valued is based on snooping or processor operations. For processor operations the accessed or to be accessed way is set as the MRU, while in snoop operations, the way being accessed is set as the LRU. The aging of the remaining ways is shuffled accordingly. This shuffling occurs each cycle but is only stored on processor cache hit, processor read cache miss and snoop hit operations.

Abstract: An apparatus which receives locking signals from a first device and provides a lengthened version of certain of these signals to a second device. The apparatus stretches the locking signal provided to ensure that the signal remains valid throughout the entire locked sequence. The apparatus also indicates when arbitration windows are available between back-to-back locked cycles, i.e. when it is okay to relinquish control of the host bus to a requesting bus master or device. The apparatus monitors cache controller activity and notifies arbitration logic when the last write cycle of a read-modify-write sequence or multiple transfer write cycle begins. When the cycle completes, the arbitration logic releases the bus, thus providing an arbitration window for other requesting bus masters and devices. In this manner, overlock conditions which block bus masters from obtaining control of the bus are prevented from occurring.

Abstract: An attachment unit interface electrical connector which includes a slide latch which is moveable between open and close positions utilizing a pivotally mounted tab member. The pivotally mounted tab member is mounted onto the slidably mounted latch so that the latch member is accessible even when the attachment unit interface female connector is attached to a male connector in an area of confinement.

Abstract: An EMR reduction technique using grounded conductive traces and vias circumscribing the internal planes of printed wiring boards. Conductive vias are placed in a circuitous path near the border and encircling the signal traces of each layer of a printed circuit board. The ground plane is extended to encompass and electrically ground each of the vias. For each signal plane, a conductive trace is routed and connected to each of the vias forming a grounded shield around the signal-carrying traces on the signal plane. For the power planes, a conductive trace is also provided connecting the conductive vias and forming a grounded shield around the power planes. A non-conductive path is provided between the power plane and the power plane conductive trace to electrically isolate the voltages of the power plane from the grounded conductive trace.

Abstract: A battery charge controller and fuel gauge which accurately monitors the voltage, temperature, and charge and discharge current of a rechargeable battery, and calculates the battery's charge capacity and charge level. Each time the battery is fully discharged, any calculated charge level remaining is divided by two and subtracted from the previously calculated charge capacity. When the battery is fully charged, the charge level is set equal to the charge capacity. During subsequent charge and discharge, the current is converted to a coulomb count and added or subtracted from the charge level to maintain an accurate charge level. Fast charge inefficiency due to temperature is considered by subtracting a temperature proportional factor before the charge level of the battery is updated. The charge level, voltage and temperature are used to determine the optimal fast charge termination point to achieve full charge and prevent temperature abuse and overcharge.

Abstract: A graphical display icon on the front of a data storage unit provides status information on disk drives within the unit. The icon has a shape identical to that of the unit and includes a number of bicolor LED's which each correspond to a similarly situated disk drive located in the unit. The color emitted by the LED's communicate information on the status of the corresponding disk drive within the unit.

Abstract: A computer system has a processor coupled to a cache controller, uses page mode memory devices and performs page hit detection on the processor local bus. Column address and data values are latched by a memory controller on memory write operations to allow early completion of the cycle so that the next cycle can partially overlap. This allows the use of economical memories and yet have zero wait state page hit operation.

Abstract: At least two double buffers or FIFOs, each FIFO including a first group of latches in series with a second group of latches, coupled between a host data bus and a corresponding bank or way of interleaved memory. The inputs of the first group of latches are coupled to the host data bus, and the inputs of the second group of latches are coupled to the outputs of the first group of latches of each double buffer or FIFO. The outputs of the second group of latches are coupled to the memory data bus of the corresponding way of interleaved memory. During a burst write sequence, an address is placed on the host address bus and a series of data doublewords are sequentially placed onto the host data bus, while the DRAMs of main memory are entering into page mode. The first group of latches of each double buffer or FIFO latches in every other data doubleword.

Abstract: An apparatus for determining system configuration in a computer system using only one 8 bit data port. Permanent connections on each of the microprocessor and memory boards provide respective configuration and/or memory information about each board. The signals are stored in serial out shift registers associated with each board that are daisy chained together. These shift registers serially transmit the configuration information to one 8 bit data port, which then transmits this information to the computer system in 8 bit increments. If a given slot is empty it is automatically bypassed in the shift register daisy chain.

Abstract: A method for performing buffer copy operations in a personal computer system utilizing paged memory mode architecture and having a cache memory. The contents of a first buffer are read into a microprocessor register and simultaneously written into a cache memory. The first buffer is then read again and written to a second buffer, with the actual data values being obtained from the cache memory. This method avoids excessive wait states associated with changing memory pages from the first buffer memory address to the second buffer memory address for each data value.

Abstract: A communication system including one or more host adapters connected to a host computer, each adapter having multiple serial communication ports for transferring data between the computer and several TTY devices. Several of the adapter's serial ports include a high speed serial link for communicating with a data concentrator. The adapter automatically detects the presence of a concentrator connected to a switchable port and switches to the high speed link. Each concentrator includes multiple serial ports for communicating with TTY devices, and a high speed serial link for communicating with the adapter's high speed link. The concentrators allow more than one TTY device to share a single adapter serial port. Data from all of the TTY devices is accumulated into an adapter data buffer during a configurable time period or until a certain amount of data is accumulated, at which time the adapter interrupts the computer and transfers the accumulated data to the computer in one transfer operation.

Abstract: A pixel color processor that performs supplemental graphical processing duties in a video unit in a computer system. The pixel color processor is interfaced between a processor and video memory and performs pixel string manipulation and color management duties on the pixel color data at the direction of the processor, thereby freeing up the processor of these duties. The memory address space of the processor includes a monochrome memory area which maps onto the full-depth packed-pixel video memory. When the processor performs operations on this monochrome area, the pixel color processor intercepts the addresses data generated by the processor and performs the pixel block transfers.

Abstract: Two independently operating microprocessors share common control, data and address buses. A first of the microprocessors is assigned, when it is on the buses, to respond to all maskable interrupts by causing placement of an interrupt vector on the bus at the start of the next bus cycle. When the second microprocessor is on the buses and a maskable interrupt is received, the start of the next bus cycle is inhibited from causing an interrupt vector to be placed on the bus.

Abstract: A SCSI bus controller which has a separate data path from the SCSI bus to the host bus and a separate command path for use to communicate with a local microprocessor. The local microprocessor is connected to a dual port RAM, the other port of which is connected to a bus master controller linked to the host system. Commands and status are passed via the dual port RAM. Data is passed through a FIFO. The local microprocessor does not have access to the data path but only controls direction of the data flow, the initiation of the sequence and the completion of the sequence.

Abstract: A system utilizes one or more programmable logic arrays or gate arrays for regulating the commands available to a microprocessor, and intercepting certain of those commands according to predetermined citeria. The system selects and processes designated commands relating to the FORCE-A20 signal and CPU-RESET signal for a keyboard controller functionally attached to an INTEL 80286 or 80386 microprocessor. The system includes one or more programmable logic arrays or gate arrays for allowing all input commands to pass directly through to the keyboard controller except the command sequence relating to the FORCE-A20 signal or the CPU-RESET signal.