Abstract: A method and apparatus which reduces the non-snoop window of a cache controller during certain operations to increase host bus efficiency. The cache controller requires a bus grant signal to perform cycles and cannot snoop cycles after the bus grant signal has been provided until the cycle completes. Cache interface logic monitors the cache controller for cycles that require either the expansion bus or the local I/O bus. When such a cycle is detected, the apparatus begins the cycle and does not assert the bus grant signal to the cache controller. The cache controller thus believes that the cycle has not yet begun and is thus able to perform other operations, such as snooping other host bus cycles. During this time, the cycle executes. When the read data is returned or when the write data reaches its destination, the interface logic provides the bus grant cycle to the cache controller at an appropriate time. By delaying the bus grant signal in this manner, the non-snoop window is reduced.

Abstract: A method for improving SCSI controller operations by actively patching SCSI processor instructions. In a first case, tag values assigned to queues for tagged queue operation are a multiple of the SCSI processor jump instruction length. When reselected, the tag value is patched or overwritten as the least significant byte of the address of a jump instruction. The upper bytes point to the beginning of a jump table. Each entry in the jump table is a jump instruction to the sequence for a particular queue or thread. Thus simple entry is made to the desired thread without a conditional branch tree. In a second case, special SCSI operations are directly handled by the host device driver and the SCSI processor only performs conventional data transfers and similar operations. The device driver patches the message length of the SCSI processor code to an illegal value, so that an illegal instruction develops, prompting the host device driver to perform the operation at a register level.

Abstract: A computer system provides a 48-bit timer having 120 ns resolution and possessing a rollover period in excess of one year. The preferred embodiment includes two system data buffers (SDBs), each of which includes a full 48-bit timer. The timers are synchronized, and the output of each timer is provided to the host bus in alternating pairs of bits, so that half of the data bits are provided by the first SDB and half of the timer bits are provided by the second SDB. The timer may be read either as a 48-bit timer or a 32-bit timer.

Abstract: A battery pack for a portable or notebook computer which substantially eliminates hard wiring components including a generally rectangular housing having an opening in the bottom. The opening in the bottom receives a support chassis which mounts a series of electrical contact points for interfacing with the main computer housing. The support chassis mounts a printed circuit board which receives the electrical contact points for electrical connection to the various components of the printed circuit board such that electrical connection is made between the array of batteries and the main computer housing utilizing a series of electrical surface contact points rather than hard wiring, which preserves space and reduces manufacturing costs.

Abstract: A boot strap control circuit including a depletion mode NMOS transistor to effectively switch a boot strap bleed resistor out of the circuit after power up is achieved. The NMOS transistor is initially turned fully on to allow current to flow through the bleed resistor to a pulse width modulation circuit (PWM) upon power up and to allow early control by the PWM. When the PWM reaches operating power, it asserts its reference voltage output high, activating a transistor switch to turn the NMOS transistor fully off. A capacitor maintains power to the PWM until an auxiliary winding of the power transformer develops sufficient voltage to operate the PWM. In the event of failure of the auxiliary winding, the NMOS transistor operates discretely, turning on and off at a low duty cycle, rather than operating in the linear mode. In this manner, the NMOS transistor and bleed resistor assure low power during normal operation and safe operation at all times.

Abstract: A capacitor mounting structure for printed circuit boards wherein the capacitor includes first and second terminals which are connected to first and second conductor planes in the printed circuit board. Three vias are mounted in the printed circuit board in a position to be aligned with the middle of the capacitor. A first conductor pad is mounted underneath one end of the capacitor and includes spaced apart extension portions which electrically attach to the first and third via. A second conductor pad is mounted under the other end of the capacitor and includes a central extension portion which attaches to the second or middle via. In this manner, the region available for generation of parasitic inductance is minimized thereby increasing the operating efficiency of the capacitor.

Abstract: A computer system with a digitizer based screen display in which the digitizer data is buffered through a first-in first-out memory (FIFO). The processor is only interrupted when a full digitizer data packet is available in the FIFO, rather than being interrupted on each data byte available in the FIFO. The FIFO can hold multiple digitizer data packets, so that data is not lost should the processor in the computer system be unable to immediately handle these digitizer data packets. The system also provides a filter in a separate controller that examines each digitizer data packet to determine if the pen is in a predefined screen location that performs a prespecified function. If so, rather than pass the digitizer data packet to the system processor through the FIFO, the command is passed through a separate register to the processor based on the "hotspot" touched on the screen.

Abstract: A power converter including a complementary regeneration circuit for eliminating oscillations and conserving leakage energy to increase the efficiency of a flyback power converter. The complementary regeneration circuit includes a regeneration capacitor, a regeneration switch, a diode and appropriate timing circuitry to switch the regeneration capacitor in and out of the circuit at the appropriate times. Due to the operation of the regeneration switch, the capacitance of the regeneration capacitor is much larger than a typical snubber/clamp capacitor, so that it overdamps the circuit eliminating voltage overshoot typically appearing across the primary switch. The regeneration capacitor charges with regeneration energy and drives negative current into the primary inductor, holding the voltage across the primary switch constant when the secondary current goes to zero.

Abstract: A circuit that automatically detects whether an input/output expansion board is connected to an EISA system or an ISA system. The circuit monitors the expansion bus for EISA slot-specific I/O cycles by sampling the bus signals AENx and BALE when either of the IORC, or IOWC, signals are asserted. When the circuit detects an EISA slot-specific I/O operation on the expansion bus, a signal is generated indicating that the expansion bus is the EISA bus. This determination allows an ISA expansion board to take advantage of certain EISA features when it is connected to an EISA system. Using a circuit to determine expansion bus type removes the need for a jumper to provide the same function, thus providing greater ease of use.

Abstract: An method and apparatus for determining and selecting configuration options and settings of circuit boards used in a computer system. The options and settings are placed in a file according to a given format, at which time the system determines if non-conflicting use of the common system resources is possible. The method and apparatus also provide for definable linking resources which further define relationships between various boards within a computer system and the allocation of common computer resources to the circuit boards. The method also decreases the time required for the computer to resolve linking resource and common computer resource allocation conflicts by processing only those resource requirements required to resolve the conflict.

Abstract: A system for monitoring performance of an intelligent array expansion system includes a controller for communicating with a host computer and associated intelligent array expansion systems, each of which has a plurality of fixed disk drives. The controller incorporates firmware to monitor a plurality of predetermined performance data, such data being thereafter stored in information storage devices. At the same time counts are maintained for selected parameters which are of interest to a systems manager. Such counts and the performance data are stored for each one of a plurality of preselected intervals, and an indication or warning is given to the systems manager when performance data, or when a selected parameter exceeds a preselected threshold.

Abstract: A host computer including a posted write cache for a disk drive system where the posted write cache includes battery backup to protect against potential loss of data in case of a power failure, and also including means for performing a method for determining if live data is present in the posted write cache upon power-up. The posted write cache is further mirrored and parity-checked to assure data validity. Performance increase is achieved since during normal operation data is written to the much faster cache and a completion indication is returned, and the data is flushed to the slower disk drive system at a more opportune time. Batteries provide power to the posted write cache in the event of a power failure. Upon subsequent power-up, a cache signature previously written in the posted write cache indicates that live data still resides in the posted write cache. If the cache signature is not present and the batteries are not fully discharged, a normal power up condition exists.

Abstract: An apparatus for conditioning signals output from a computer system expansion card to a computer system board to test system board bus specifications and timing limits. The apparatus comprises two signal conditioning extension cards which are used to condition signals from a slave card and a bus master card. The signal conditioning extension cards according to the present invention are interposed between the bus master or slave expansion card and the system board and selectively advance or delay the signals output from the expansion card to the system board. The slave signal conditioning card also selectively delays the read data valid window of the slave card to test the limits of the system board. The bus master signal conditioning card selectively delays the write data valid window of the bus master card to test the limits of the system board.

Abstract: A circuit for connecting the power supply output of a computer to ground when the system is shut down to counter adverse effects of backfeed voltage which includes a MOSFET between the power supply output and ground. In one embodiment the MOSFET is switched on by a signal that deactivates the system power supply. In an alternative embodiment, two MOSFETs are used. The first MOSFET is controlled directly by the power supply output and shorts the second MOSFET's gate to ground when the power supply output generates a significant voltage. If the second MOSFET's gate is grounded, the MOSFET deactivates and opens a circuit between the power supply output and ground. When the power supply is turned off, the second MOSFET activates and grounds the power supply output. A resistor between the power supply output and ground allows the power supply to generate five volts when the system is power cycled and deactivate the second MOSFET.

Abstract: A card extender unit for a computer housing including first and second card extender sections which mount the card extender in position in the computer housing. The card extender includes a housing including first and second sections which support a printed circuit board having one or more high wattage, integrated circuits. One of the card extender sections includes a flow direction channel intake for directing air generated by an internal housing fan over one or more of the high wattage, integrated circuits mounted on the printed circuit board.

Abstract: A soft switching circuit gradually connects an audio signal to zero reference level to mute the audio signal, or connect a filter to enable the filter. A MOSFET is connected between the audio signal and the zero reference level. A resistor-capacitor circuit is connected to the gate of the MOSFET and receives the MUTE or FILTER* signal from the computer system. When the MUTE or FILTER* signal changes condition, the RC circuit provides a signal to the MOSFET gate that changes relatively gradually. Consequently, the drain-to-source resistance of the MOSFET also changes from short circuit to open circuit or vice versa relatively gradually.

Abstract: The present invention includes two variations of an apparatus which generate a version of the IORC* bus signal that is supplied to the read strobe input of a floppy disk controller that is asserted at the appropriate time during verify cycles between the floppy disk controller and a DMA controller. These designs allow an 82077 floppy disk controller to operate properly in FIFO mode when it is being used with software that does not require generation of this signal. The designs include use of a PAL and certain bus signal inputs to generate a signal which is asserted at the appropriate times during verify transfers. This signal is combined with the regular IORC* bus signal to produce the signal that is provided to the read strobe input of the floppy disk controller.

Abstract: An apparatus which converts burst mode bus cycles into single cycle mode cycles and converts separate address and data strobe signals into a single address strobe in a computer system. The apparatus also receives an address strobe signal, a number of address signals and the length of the burst when a device begins a burst cycle. After the first cycle of the burst transfer is complete, the apparatus initiates each subsequent cycle comprising the burst transfer by incrementing the address signals and providing additional address strobe signals until the burst is complete. The logic also facilitates address pipelining by monitoring a next address signal generated by the device. The apparatus monitors the separate address strobe and data strobe signals and generates the single address strobe signal on the next clock cycle after the address and data strobe signals are asserted.

Abstract: For use with a computer system having an intelligent mass storage disk array subsystem, including a microprocessor controller, a method for the distribution of data within the disk array based upon logical commands issued by the computer system. The disk controller reads a logical command and translates the commands into multiple drive specific commands, including drive physical parameter information such as head, sector and cylinder selection. The calculation of these physical parameters is based upon a number of factors including the operating system installed in the computer system, the type of interleave scheme, if any, specified by the computer system configuration, and disk specific parameters. The physical drive requests are then placed in a queue and executed by the microprocessor controller.

Abstract: A method and apparatus for operating tightly coupled mirrored processors in a computer system. A plurality of CPU boards are coupled to a processor/memory bus, commonly called a host bus. Each CPU board includes a processor as well as various ports, timers, and interrupt controller logic local to the respective processor. The processors on one or more CPU boards are designated as master processors, with the processors on the remaining CPU boards being designated as mirroring or slave processors. A master processor has full access to the host bus and a second, multiplexed bus for read and write cycles, whereas the slave processors are prevented from writing to any bus. The slave processors compare write data and various control signals with that generated by its respective master processor for disparities.