Abstract: A system management mode address correction system for a computer provides correct address values on the address bus when the computer is in system management mode. Conventionally, bit 20 of the microprocessor's address outputs may be masked by asserting the FORCE A20 signal. The computer system also operates in a system management mode, which requires all of the address bits to be available for proper access to the system management interrupt vector. When the computer is in system management mode, the computer's microprocessor asserts a system management interrupt active (SMIACT*) signal. This signal is provided to a circuit which also receives the FORCE A20 signal. While the SMIACT signal is deactivated, the control circuit provides the true FORCE A20 signal to the computer system. When an SMI occurs, the SMIACT signal is activated and the FORCE A20 signal is disabled. As a result, the address generated by the microprocessor is asserted on the address bus.

Abstract: A system for mapping a PCI interrupt signal to any EISA interrupt signal, in which sharing is allowed between PCI interrupts as well as between a PCI interrupt and an EISA interrupt. The actual mapping is performed during the Power On Self Test (POST) procedure, where the computer writes appropriate values into a set of MAP and MASK registers. Each MAP and MASK register corresponds to a PCI interrupt. Thus, by programming the appropriate MAP and MASK register to certain values, the corresponding PCI interrupt can be mapped to the desired EISA interrupt signal. A decode logic then produces a set of final interrupt signals based on the state of the PCI interrupt signals, the MAP and MASK registers, and the EISA interrupt signals. The final interrupt signals are provided to an interrupt controller, which responds to the assertion of the final interrupt signals by asserting an interrupt signal to the microprocessor.

Abstract: A power switch circuit including a small signal transformer and a low power oscillator for detecting the power switch while isolating it from the primary of the power supply. When the power switch is off, or is otherwise pressed to turn off the power supply, the oscillator charges a capacitor. A sensing and control circuit coupled to the oscillator and capacitor grounds a vital signal of the power supply keeping the power supply turned off. In one embodiment, when the switch is turned on, it shorts the signal transformer disabling the oscillator, so that the capacitor is discharged and the sensing and control circuit releases the vital signal. In another embodiment, the power switch momentarily disables the oscillator and discharges the capacitor, so that the sensing and control circuit toggles a flip-flop circuit to turn on the power supply.

Abstract: Two design variations which allow multiple processors to start up using a single ROM. In each design, a single, primary processor is allowed to perform a complete POST while the remaining, secondary processors are directed in the course of their POST to perform a more limited initialization sequence. At power on, the primary processor begins a normal POST, while the secondary processors are held until a vector is placed into a redirection vector location. Each secondary processor is then subsequently started, using its own initialization code located at the address indicated by the redirection vector. The first technique is applicable to general multiprocessor systems because the implementation of this design can be run either from external software or from an addition to the operating system of the particular machine on which it is being used.

Abstract: A method that identifies the type of LCD panel used in a portable computer system based on the frequency of the oscillator signal of the DC-to-AC inverter in the LCD panel. In this method, only one signal is routed from the LCD panel to the base unit of the portable computer system for the purpose of panel identification. The inverter oscillating signal is used to increment a counter during power on operations. A system counter, which is clocked by a system clock, is used to determine the number of system clocks needed for the panel identification counter to reach a predetermined count. That number is compared with the entries of a table, in which each entry corresponds to a type of LCD panel. In this manner, the type of LCD panel can be identified based on the frequency of the inverter signal. A corresponding entry in a second table is accessed to obtain a table entry for the identified LCD panel to a full table of LCD panel parameters. The table entry is stored in a predetermined location in the Video ROM.

Abstract: A hot spare boot circuit that automatically switches from a non-operational CPU to an operational CPU for powering up the computer system. In the multiprocessor computer system, a first CPU is designated to perform power on operations. If the first CPU fails, which is determined when a dead man counter in the hot spare boot circuit times out, the hot spare circuit ensures that the first CPU is in a disabled state. Next, the hot spare boot circuit identifies an operational second CPU, reinitializing certain ID information as necessary such that the second CPU can properly perform power on operations. The hot spare boot then awakens the second CPU, using a startup interprocessor interrupt in one embodiment, or simply negating the hard reset of the second CPU in a second embodiment. The second CPU then proceeds to perform the power on functions.

Abstract: A low quiescent current voltage regulator particularly suited for providing current to the RTC/CMOS memory section of a notebook computer. The gate of the JFET is grounded, the drain connected to the main battery and the source connected to the RTC voltage input of the RTC/CMOS memory section. The JFET source voltage approaches the gate-source cutoff voltage of the JFET. This cutoff voltage is selected to be in the proper range for the RTC/CMOS memory section. A complete RTC voltage control circuit is configured to provide 5 volts from the system voltage when the computer is turned on, 3 to 5 volts from the JFET when the computer is turned off and the main battery is present and 3 volts from the RTC battery when the computer is turned off and the main battery is removed.

Abstract: A multiprocessor computer system handles the failure of one or more of its processors without totally disabling the system. On power up, all of the CPUs are deactivated except for a CPU in a first physical slot. The power on self test routines review a log of errors and determine if certain critical errors have previously occurred. If so, the CPU in the first physical slot halts operation entirely. If the CPU in the first physical slot is not functioning properly or is halted, the hardware then awakens a CPU in a second physical slot, designates it as the first logical CPU, and the CPU then performs similar diagnostic checks. If it fails, the hardware again tries a third physical CPU and so on. When one CPU passes the initial error review, it proceeds with initialization of the computer system and performs further self testing. If it functions properly, it is designated as the first logical CPU, and retains its designation until the power is cycled.

Abstract: A computer system includes an error detection and correction system for detecting and correcting single-bit errors, two-adjacent-bit errors, and four-adjacent-bit errors. Two identical error detection and correction (EDC) circuits are connected to the system memory array, and each EDC circuit is connected to half of the data bits in alternating pairs. Each EDC circuit detects single-bit errors and two-adjacent-bit errors. The EDC circuits are connected to alternating pairs of data bits so that errors of up to four adjacent bits are actually detected and corrected, two bits by the first EDC circuit and two bits by the second. Thus, if one of the x4 DRAMs in a memory array fails, each erroneous data bit from the DRAM is corrected to its original value, and the failure of the DRAM is registered.

Abstract: A notebook computer system for docking to a motorized expansion base unit. Before the actual docking event occurs, the notebook computer system communicates with the expansion base unit via a sense signal, which is provided by the notebook computer to indicate the power state of the notebook computer. If the expansion base unit determines that the notebook computer is in a proper state for docking, it activates its motor to load the notebook computer. Once docked, the notebook computer runs a resource conflict check routine to determine if resource conflicts occur. A fatal conflict occurs when the resource requirements of bus devices connected to the expansion base unit conflict with the resource requirements of a video controller or hard disk drive connected to the notebook computer. When such a fatal conflict occurs, the notebook computer issues a software eject request to expansion base unit. In response, the expansion base unit undocks the notebook computer.

Abstract: A power supply monitoring and control circuit using a microcontroller to remotely monitor and control the functions and conditions of a power supply. The power supply monitoring and control circuit is coupled to the primary and secondary sides of a power supply to monitor important voltage and current signals of the power supply, such as the output voltages and currents, and to control the various parameters of the power supply such as the output voltage and current limits. Analog to digital interface circuitry is provided to convert the power supply voltage and current signals to digital signals which are retrieved by a microcontroller which converts the digital signals to numbers representing the values of the power supply signals, and then stores the numbers. The microcontroller is also interfaced to reference and feedback signals of the power supply to control the power supply's operation.

Abstract: A synchronized switch tapped coupled inductor circuit which couples a first closed-loop regulated output of a forward converter switching power supply to a second output to assist in regulating the voltage of the second output. The switched power supply includes a converter transformer which is implemented as a forward converter providing the multiple outputs. The second output includes a storage inductor which is coupled to a storage inductor of the first output. The second coupled inductor includes a center tap which is connected to a synchronized switch. The synchronized switch is further connected to the first output and coupled to the converter transformer to detect the forward and flyback portions of each cycle. During the flyback portion of each cycle, the switch is turned on coupling the center tap to the first output. During the forward portion of each cycle, the switch is turned off, isolating the outputs from each other.

Abstract: A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller can utilize different speed memory devices at their desired optimal speeds. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine reaches has completed its function, it notifies a related state machine that it can now proceed and proceeds to wait for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks.

Abstract: A switching circuit controls the routing of various signals of the computer system to and from the various pins of a microprocessor socket. A microprocessor rests in the socket and can be removed and replaced by another microprocessor. Variations in the pin arrangements of the two processors can be compensated for by appropriately setting the switches on the processor card. The use of 486SX, 487SX and 486DX microprocessors is illustrated in a single socket.

Abstract: An arbiter which allows retried requests to have high priority in subsequent arbitrations by not changing priority on a granted, but aborted, access to the bus and yet prevents the aborted requestor from thrashing the bus by masking its bus request signal until the data is available. Further, should an access to main memory be retried, all bus requests except the one from the memory system are masked to provide the memory system the highest effective priority to allow any flushing operations to occur. The masking of the various bus requests allows the arbiter to control access to a PCI standard bus without requiring that specific signals be added. The arbiter further includes modified priority LRU techniques and provides a locking requestor with an additional, highest priority position if retried.

Abstract: An efficient fan drive circuit to drive a variable fan used in a power supply of a personal computer system. The fan drive circuit uses a diode to establish the minimum fan speed during operation in the normal temperature range. The bleeder resistor normally coupled between the fan and a negative output voltage is removed and replaced with a current source. The current source also serves to shut down the power supply if the fan is not operating properly or is not installed. A shut down circuit remains to shut down the power supply when excessive temperature occurs, or when the current source detects that the fan is malfunctioning or not installed.

Abstract: A computer system determines the presence of a device on the system bus that responds to I/O or memory reads by performing an I/O or memory read with data bus pulled to its normally undriven state. If the value returned is other than the data bus' normally undriven value, it is determined that a device is responsive to that I/O or memory read. Otherwise, the system then pulls the data bus to other than its normally undriven state and performs another I/O or memory read. If the value returned is again the value of the data bus' normally undriven state, it is determined that a device is present because it is driving the data bus back to its normally undriven state. Otherwise, it is determined that a device is not driving the data bus in response to an I/O or memory read. Further, the computer system according to the invention makes the determination of whether a device is driving the bus using a comparator to compare the level present on the data bus in response to the I/O or memory reads.

Abstract: A communication system including one or more host adapters connected to a host computer, each adapter having multiple serial communication ports for transferring data between the computer and several TTY devices. Several of the adapter's serial ports include a high speed serial link for communicating with a data concentrator. The adapter automatically detects the presence of a concentrator connected to a switchable port and switches to the high speed link. Each concentrator includes multiple serial ports for communicating with TTY devices, and a high speed serial link for communicating with the adapter's high speed link. The concentrators allow more than one TTY device to share a single adapter serial port. Data from all of the TTY devices is accumulated into an adapter data buffer during a configurable time period or until a certain amount of data is accumulated, at which time the adapter interrupts the computer and transfers the accumulated data to the computer in one transfer operation.

Abstract: A disk array controller board which utilizes an EISA bus master which is a slave on its internal data bus to allow an advanced drive array controller chip (ADAC) to operate as a master. The ADAC is connected to transfer buffer RAM. The protocol of the internal data bus provides for a cycle to load a host memory address into the bus slave, to provide transfer count information and slave specific information and for a series of data transfer cycles. The local processor is connected to the EISA bus master and the ADAC to control operations and to provide certain information. The ADAC is controlled by structures referred to as command descriptor blocks (CDBs). Each CDB includes information which describes the various addresses, control bits and functional bits used by the ADAC to perform its transfer operations. The local processor directly writes and deposits data forming a CDB into the transfer buffer RAM.

Abstract: A method and system for independently resetting primary and secondary processors 20 and 120 respectively under program control in a multiprocessor, cache memory system. Processors 20 and 120 are reset without causing cache memory controllers 24 and 124 to reset.