Abstract: An electronic convergence device system, such as a PC/TV adapted to operate in a computer mode and a TV mode. When switching and/or operating in TV mode the top-most windows from the computer mode applications are inhibited from interfering with the TV mode experience.

Abstract: An apparatus is disclosed for protecting a computer system from an unintended or a malicious removal of power by a user. The apparatus has a power supply for supplying power to the computer system, a non-volatile memory to store a shutdown key for authorizing a shutdown of the power supply, and a power supply shutdown circuit connected to the power supply and the non-volatile memory. The power supply shutdown circuit also includes a switch adapted to receive a power supply shutdown input from the user. Upon receipt of the shutdown input, the apparatus displays a dialog box which requests a password from the user. The apparatus compares the password with the shutdown key in the non-volatile memory and proceeds to shutdown the power supply if the shutdown key matches the password entered by the user. Otherwise, the apparatus maintains power to the computer system until a correct password has been entered.

Abstract: A multiprocessor computer system releases a victim data buffer storing victim data, when system control logic determines that a count of the number of probe messages pending at a specified time equals the number of such probe messages that have had an address comparison performed after the specified time. The specified time occurs when a command to write the victim data element to main memory passes a serialization point of the computer system.The address comparison compares a target address of a probe message with addresses of data stored in the victim data buffer and the associated cache of a CPU of the computer system.

Abstract: A method for performing 16 Bit BIOS interrupt calls under a 32 Bit protected mode application. This has been impossible to-date and has forced BIOS development teams to add support into the BIOS for 32 bit function calls from 32 bit applications.

Abstract: The present invention is directed to apparatus and methods for reducing transient signals in phase locked loop (PLL) circuits of central processing units. One aspect of the present invention is directed to a method and apparatus that disables a charge pump circuit in a phase locked loop circuit when a frequency change in the output signal of the PLL circuit is implemented to limit transient signals generated by the PLL. Another aspect of the present invention is directed to a method and apparatus for coordinating a change in divider values for frequency dividers in a PLL of a CPU to limit transient signals from the PLL.

Abstract: A computer system includes a timer which times out if the operating system does not periodically reset the timer. When the system fails and no longer resets the timer, the timer times out, and the computer is reset. The system performs its power on program and checks the memory array for bad memory blocks, which are mapped out of the memory. Next, the system alerts the operator of the failure using a pager. The system then reboots itself from a hard drive having two separate bootable partitions, one for the operating system in the first partition, and one for a diagnostics program in the second partition, so that an operator may diagnose and remedy the problem. The operator may set an indication of which partition to use for booting. The system further provides for remote access so that the operator may interact with the diagnostics program from a remote location.

Abstract: A method and apparatus which indicates the physical location of one or more peripheral devices. A system operator uses an input device to select an icon that is displayed on a display device. The icon represents a single peripheral device or a group of peripheral devices among a plurality of peripheral devices. For example, an icon may represent a disk drive, a group of disk drives disposed within a storage unit, an array of disk drives, an array of disk drives disposed within one or more storage units, etc. After the system operator selects the icon, an indicator light associated with each of the one or more peripheral devices represented by the icon illuminates to identify the physical location of the selected peripheral device or devices. Other peripheral devices are contemplated, such as a bank of modems, floppy drives, CD-ROM drives, etc.

Abstract: A method for use in connection with resetting a CPU including requesting a first reset code stored in an inaccessible memory and redirecting the request to a second reset code stored in accessible memory.A computer system including a CPU, a first memory that may become inaccessible, and a CPU reset facilitator configured to respond to a reset request from the CPU to the first memory at a time when it is inaccessible by diverting the CPU to a second memory.

Abstract: A method for powering up a removable circuit card when it is inserted into a card slot of a computer system includes providing power and a clock signal to the circuit card. A communication link is electrically coupled to the circuit card after both the power and the clock signal are provided to the circuit card.

Abstract: An apparatus and method a method for performing two-pass real time video compression is provided. Tactical decisions such as encoding and quantization values are determined in software, whereas functional execution steps are performed in hardware. By appropriately apportioning the tasks between software and hardware, the benefits of each type of processing are exploited, while minimizing both hardware complexity and data transfer requirements. One key concept that allows the compression unit to operate in real time is that the architecture and pipelining both allow for B frames to be executed out of order. By buffering B frames, two-pass motion estimation techniques can be performed to tailor bit usage to the requirements of the frame, and thereby provide a more appealing output image.

Abstract: An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory.

Abstract: A self-locking mounting method and apparatus are disclosed. A self-locking mounting apparatus comprises a bracket for holding a storage device, a chassis having at least one flange for supporting the bracket, a retaining mechanism which engages the bracket upon insertion of the bracket into the chassis. The retaining mechanism may include a tab on the chassis and at least one latch on the bracket. The latch may be a spring latch. A plurality of flanges protruding from the chassis may be used to support the bracket. A method for mounting a self-locking apparatus includes the steps of attaching a storage device to a bracket, inserting the bracket into a chassis, the bracket being supported by at least one flange on the chassis, and engaging the bracket to the chassis with a retaining mechanism.

Abstract: A computer system includes a CPU and a memory device coupled by a North bridge logic unit to an expansion bus, such as a PCI bus. A South bridge logic connects to the expansion bus and couples various secondary busses and peripheral devices to the expansion bus. The South bridge logic includes internal control devices that are targets for masters on the expansion bus. The target devices couple to the expansion bus through a common expansion target interface, which monitors and translates master cycles on the expansion bus on behalf of the target devices. The South bridge also includes an internal modular target expansion bus coupling the internal target devices to the common target interface. The internal modular target expansion bus permits the target devices to receive master cycles from any expansion bus by understanding a standardized group of signals represented by the internal modular target expansion (IMAX) bus.

Abstract: A method and related apparatus enables one station on a local area network (LAN) 24 to securely wake up another station on the LAN 24 although the stations may be physically remote from each other. A workstation 12, acting as a remote management console, generates a secure wake-up packet 42 intended for a desktop computer 14 on the LAN 24. The desktop computer 14 is operating in a sleep state. The data section of the secure wake-up packet has a particular sequence of data including a synchronization sequence 46, a MAC address sequence 48 and a password sequence 50. The desktop computer 14 has a network interface 64 for detecting and processing secure wake-up packets 70 when that network interface 64 is operating in a remote access control mode. The network interface 64 verifies that MAC address sequence 48 corresponds to the MAC address of the desktop computer 14 and that the password sequence 50 has a predetermined relationship with a password required to wake up the desktop computer 14.

Abstract: A SCSI bus arbitration controller includes a hub to which each of the SCSI devices having access to the bus is connected. The hub includes a controller that monitors the data lines on the bus, as well as the BUSY and SELECT lines. The hub also includes a plurality of switches located between each of the devices and the data bus. For each set of device connections to a bus, the highest priority ID data line has a switch in it, as does the data line that corresponds to the ID associated with that particular device. During an initial arbitration cycle, the controller monitors the bus data lines, and determines which of the devices participate in the initial arbitration cycle. It then latches the identities of the participating devices in a register. Of the SCSI IDs of the system, the controller reserves the highest priority ID for itself.

Abstract: A cooling system for a high-end server includes four hot-pluggable fans plugged into a fan control board. The fans are arranged in two groups, with each group having two fans, one behind the other. One of the groups of fans is used to cool the processor boards and the other group is used to cool the system I/O board slots. Under normal operation, only one fan from each group is active, while the other fan freewheels, providing redundancy. A fan control board delivers power to each of the fans and further provides a signal, responsive to temperature sensors, to each of the fans to control their speeds. Each of the fans provides a fan fault signal and a fan not present signal to the fan control board. The temperature sensors are placed proximate the processors and I/O components to monitor the operating temperatures thereof, and communicate the respective temperatures back to the fan control board, via I.sup.2 C bus.

Abstract: A computer system includes a bus, remote console logic, a remote server management device, and an interrupt routing switch. The bus has a first interrupt line. The remote console logic has a second interrupt line and is coupled to the bus. The remote console logic is adapted to monitor video transactions present on the bus. The video transactions include video data. The remote console logic is further adapted to store the video data and provide an interrupt signal on the second interrupt line if the amount of stored video data reaches a predetermined threshold. The remote server management device is coupled to the bus and the first interrupt line. The interrupt routing switch is coupled to the first interrupt line and the second interrupt line and adapted to couple the second interrupt line to the first interrupt line. A method for capturing video transactions includes coupling a first interrupt line of a buffer to a shared interrupt line of a bus. Video transactions occurring on the bus are snooped.

Abstract: An electrostatic discharge protection device for protecting a mixed voltage integrated circuit against damage is provided which includes at least on pair of NMOS transistors connected in a cascode configuration. Each NMOS transistor pair includes a first transistor, having a drain region coupled to and I/O stage of the mixed voltage integrated circuit, and a gate region coupled to the mixed voltage integrated circuit's low power supply. The second NMOS transistor of the pair is merged into the same active area as the first transistor and has a gate region and a source region coupled to the ground plane of the mixed voltage integrated circuit. The source region of the first transistor and the drain region of the second transistor are constructed of a shared NMOS diffusion region.

Abstract: A technique for the automatic detection of certain characteristics of the print medium being used in a printer is disclosed. These characteristics may include, without limitation, the manufacturer, the finish, the quality, orientation, and the dimensions of the print medium. Each sheet of specialty print medium is marked at the point of manufacture or packaging with certain preassigned numeric or symbolic codes that uniquely identify the characteristics of the print medium. Sensors are added to each printer to automatically detect and decode the markings on the speciality print media. This information is used to automatically optimize the printer for the best print quality possible.

Abstract: In general, in one aspect, the invention features a system for operating the computer in any of at least two different interactive modes, along with a switch having at least two states. An access control device allows a user to change the state of the switch, for changing which interactive mode is currently active.