Abstract: A computer system includes a memory bus, a connector and a controller. The connector is configured to receive a memory module and prevent removal of the memory module from the connector in a first state. The connector allows removal of the memory module from the connector in a second state. The controller is configured to change a connection status between the connector and the memory bus in response to the connector changing from one of the states to the other state. A central processing unit of the computer system is configured to use the memory bus to store data in the memory module.

Abstract: A method is described for forming an electromigration-resistant (ER) intermetallic region beneath and adjacent a conductive plug in a via. Preferably the ER region is formed of a sintered intermetallic compound of Al and Ti, and the conductive plug is formed of W.

Abstract: A method and apparatus for allowing an Authentication Center (AC) in a cellular telephone system to store and access event a predefined number of maintenance data events on a per-MIN/ESN basis.

Abstract: A programmable arbitration system including control logic to select one of several arbitration schemes for selecting the ports of a network switch, a memory to store priority values indicating the relative priority of each of the ports, monitor logic to monitor each of the ports and to program the priority values in the memory based on a priority scheme selected by the control logic, and arbitration logic to select a port having the next highest priority. The arbitration schemes preferably include a round-robin priority scheme, a first-come, first-served (FCFS) priority scheme, a weighted priority scheme, or any other desirable priority scheme. The monitor logic includes polling logic to periodically poll the ports and to program a priority value of each port. The memory includes receive and transmit lists to indicate of which of the ports have indicated needing service and a corresponding priority value.

Abstract: A technique for speculatively issuing instructions using an out-of-order processor. A cache miss by a load instruction results in either a reissue of all subsequently issued instructions for an integer instruction stream, or a reissue of only truly dependent instructions for a floating point instruction stream. One version of the technique involves issuing and executing a first instruction, and issuing a second instruction during a speculative time window of the first instruction that occurs after the first instruction is issued. The technique further involves executing the issued second instruction when the first instruction is executed in a first manner, and reissuing the second instruction and executing the reissued second instruction when the first instruction is executed in a second manner that is different than the first manner.

Abstract: A network switch including a plurality of first network ports, a plurality of second network ports, a first bus, a second bus and a bridge interface coupled between the first and second buses. The first ports receive and transmit network data according to a first network protocol and the second ports receive and transmit network data according to a second network protocol. The first and second buses operate according to different bus standards. The bridge interface enables data transfer between the first and second buses and thus between the networks operating at different protocols. The switch includes a switch manager that controls the flow of network data and a processor for performing supervisory and control functions. The bridge interface includes receive buffers and transmit buffers assigned to respective ports. During packet data transfer operations across the first bus, the bridge interface emulates a first network port.

Abstract: A single overvoltage, overcurrent, and overtemperature protection circuit for use in an off-line switched-mode power converter using current-mode pulse-width modulation control. A single latch circuit provides shutdown control via either voltage or current inputs of the pulse-width modulator.

Abstract: An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory.

Abstract: A network switch including a separate cut-through buffer for facilitating cut-through mode of data transfer. The switch further includes a data bus coupled to each of the ports, a memory and a switch manager coupled to the data bus and to the memory for controlling data flow. The switch manager includes a receive buffer for handling data received by the switch, a transmit buffer for handling data to be transmitted by the switch, and a separate cut-through buffer for receiving data at any of the ports and for buffering the data to another one of the ports during cut-through mode of operation. The switch manager includes status memory, which includes programmable receive and transmit mode values for each of the ports, the modes selecting between cut-through and store-and-forward mode of operation for an indicated direction for each port.

Abstract: A computer system includes an I/O controller and a bridge logic device which transmit status data via a serial bus. The I/O controller comprises an embedded controller, a memory device, and a serial bus interface including a transceiver, a transmit register, and a receiver register. The bridge logic also includes a serial bus interface with a transceiver, a transmit register, and a receiver register. Data is transmitted from the transmit register of one device to the receive register of the other device. Although the serial bus protocol limits data transfers to eight-bit segments, the I/O controller and bridge logic transmit up to twenty-four different variables by encoding each transmitted byte into a data frame that includes a two-bit frame identifier and a six-bit data field. Further, one of the data frames transmitted by the I/O controller includes an acknowledge bit to indicate when a previous frame has been received from the bridge logic.

Abstract: A method and apparatus for attaching a set of components to a printed circuit board is presented. A second board includes the set of components to be attached to the printed circuit board. The second board attaches directly to the printed circuit board by attaching to pins of a through hole device, such as an application specific integrated circuit. The through hole device is mounted on one side of the printed circuit board. The through hole device includes pins which protrude to the other side of the printed circuit board. The second board attaches to the protruding pins on the other side of the printed circuit board.

Abstract: A process for the mass production of computers where software is automatically installed according to configure-to-order requirements. Additionally, the process captures the as-built hardware and software components of each computer for the vendor service and support program. Furthermore, the process provides a software installation environment which is secure from any undetectable alteration and offers control and auditing of subcontractors who produce systems according to manufacturer's specifications. Finally, the process automates the tracking and reporting of royalty payments to the appropriate recipient.

Abstract: The Logic Analyzer Probe Board is a hardware design which allows convenient access to signals on a printed circuit board. On one side of the Probe Board assembly is a collection of probes that provide contact to the printed-circuit boards pads, pins, vias and test points on the non-component side of a UUT. The other side of the Probe Board assembly contains an organized collection of connectors, or headers, that connect to a logic analyzer's cable harness. When the Probe Board mates with the printed circuit board, the Probe Board taps into a printed circuit board's signal via the probe-to-pad connection and routes the detected signal via one of the header pins to the logic analyzer. The design of the printed circuit board includes test points that correspond to each signal under test. Once the layout of a printed circuit board is determined, a custom-designed Probe Board may be designed that is cable of accessing each test point.

Abstract: In a computer system there is a storage subsystem and an array controller circuit controlling an array of hard drives in the storage subsystem. Upon powering the storage subsystem, the array controller automatically determines whether the hard drives have been moved to new bay locations in the storage subsystem and whether a new complete logical drive, consisting of at least one hard drive, has been added to the storage subsystem. Upon discovery of any drive movement or logical drive unit addition, the array controller automatically reconfigures each hard drive by at least updating the configuration information in accordance with the changes.

Abstract: A computer system having separate, yet compatible DMA controllers on a bus. Each DMA controller for controlling at least one DMA channel, each DMA controller having an independent set of registers for performing DMA operations and a configuration register for indicating channel status and designation. A DMA master for compatibly communicating with a processor and for initializing and communicating with the multiple DMA controllers.

Abstract: A system for cooling a heat-producing component in a computer system includes a conduit or plenum and a fan assembly. The fan assembly may be supported by the conduit. An air stream directing and acoustic shielding member is disposed in the conduit to prevent or reduce transmission of acoustic noise during operation of the fan assembly to a region outside the computer console. The shield member may be made of an open-cell foam or other sound deadening or reflecting material. A secondary conduit is provided for recirculating a portion of the internal air within the computer chassis. The internal air stream may be joined and mixed with the air stream from outside the chassis to provide both fresh air and recirculation cooling.

Abstract: A carrier assembly is provided for supporting a hot-pluggable hard disk drive and is slidably and removably insertable into a sheet metal cage structure to operatively mount the disk drive therein and releasably mate an SCA connector on the drive to a corresponding electrical backplane connector within the cage. The carrier assembly includes a base wall upon which a pair of upstanding side wall structures are captively retained for pivotal movement toward and away from opposite side edge portions of the base wall. Each of the pivotal side wall structures captively retains a pair of mounting screws. With the side wall structures in their outwardly pivoted orientations, the disk drive is placed atop the base wall, the side wall structures are pivoted inwardly against corresponding opposite side walls of the disk drive, and the mounting screws are tightened into aligned threaded openings in the opposing disk drive side walls.

Abstract: An image stored in a memory of a computer as pixels, each pixel including a bit pattern to indicate a grey-scale level. The image is compressed by grouping the pixels of the image into a plurality of regularized groups of pixels. The partitioning of the image can be in groups of four by four adjacent pixels. Groups of pixels having identical bit patterns are identified. The groups of pixels are encoded according to a frequency of groups of pixels having identical bit patterns.

Abstract: A system and method to reduce power consumption in a portable computer system while allowing the CDROM drive to continue playing audio CDs. When the system enters a suspend mode, the status of the CDROM drive is checked, and if it is playing an audio CD, it remains powered, otherwise power to the CDROM drive is also suspended. The system recognizes when the audio CD is finished playing and then places the CDROM drive into the suspend mode.

Abstract: A mounting apparatus includes a bracket having plural sides adapted to accommodate a board between the sides. First fasteners on the plural sides of the bracket are disposed to connect the board to the bracket, wherein the fasteners are adapted to vertically restrain movement of the board relative to the bracket. At least one second fastener on one of the sides releasably secures the bracket to a mounting surface. A process for mounting a board on a surface includes the steps of fitting a board onto a bracket having plural sides, fastening the board to the bracket with first fasteners, and engaging a second fastener with a mounting surface. The board may be a printed wiring board or a printed wiring assembly. The plural sides may include left, right, back, and front sides. The sides may be perpendicular to each other. The first fasteners may be clips, screws, or channels found on the inside of the plural sides. A second fastener may also be included, and may be a slot, a clip, or a tab.