Abstract: A method for use in upgrading a resource of a computer from an existing version of the resource to a later version of the resource. The method includes the steps of (a) digitally storing upgrade information which identifies the later version and describes features of the later version relative to one or more earlier versions of the resource, (b) digitally storing in the computer information identifying the existing version, by computer, automatically determining which of the earlier versions is the existing version, and (c) based on the results of the comparing step, automatically determining, or displaying to a user at least some of the upgrade information to aid the user in determining, whether to perform an upgrade. The upgrade information may be stored on a portable medium along with copies of the resources and the upgrade information may include instructions, in accordance with a predefined common syntax, for installing each of the resources.
Type:
Grant
Filed:
May 11, 1998
Date of Patent:
September 28, 1999
Assignee:
Compaq Computer Corporation
Inventors:
Richard A. Stupek, Jr., David Scott Shaffer, Curtis R. Jones, Steve Davis, William D. Justice, Jr.
Abstract: A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed.
Type:
Grant
Filed:
August 28, 1998
Date of Patent:
September 28, 1999
Assignee:
Compaq Computer Corporation
Inventors:
Gary W. Thome, Michael P. Moriarty, John E. Larson
Abstract: The front side edge of the display lid portion of a notebook computer has a relatively shallow reverse draft angle of approximately five to fifteen degrees thereon and, with the display lid in its downwardly pivoted closed position on the computer's base housing, is rearwardly offset from the front side of the base housing in a manner exposing a relatively narrow front top side surface portion of the base housing. Because of the slight undercut in its front side edge resulting from the reverse draft thereon, the grasping of the front side edge, to upwardly pivot the display lid from its closed position to its open use orientation, is made appreciably easier.
Abstract: A method for enabling power to all or portions of a computer system based upon the results of a two-piece user verification process that is completed as part of a secure power-up procedure. At some point during the secure power-up procedure, the computer user provides an external token or smart card that is coupled to the computer through specialized hardware. The token or smart card is used to store an encryption algorithm furnished with an encryption key that is unique or of limited production. The computer user is then required to enter a plain text user password. Once entered, the user password is encrypted using the encryption algorithm contained in the external token to create a system password. The system password is compared to a value stored in secure memory. If the two values match, the power-on sequence is completed and power to the computer system and/or secured computer resources is enabled.
Abstract: A computer system includes a timer which times out if the operating system does not periodically reset the timer. When the system fails and no longer resets the timer, the timer times out, and the computer is reset. The system performs its power on program and checks the memory array for bad memory blocks, which are mapped out of the memory. Next, the system alerts the operator of the failure using a pager. The system then reboots itself from a hard drive having two separate bootable partitions, one for the operating system in the first partition, and one for a diagnostics program in the second partition, so that an operator may diagnose and remedy the problem. The operator may set an indication of which partition to use for booting. The system further provides for remote access so that the operator may interact with the diagnostics program from a remote location.
Type:
Grant
Filed:
December 18, 1996
Date of Patent:
September 21, 1999
Assignee:
Compaq Computer Corporation
Inventors:
David M. Burckhartt, Lazaro D. Perez, Theodore F. Emerson, Randolph O. Dow, Gary A. Stimac
Abstract: An arbitration scheme for a computer system having multiple arbiters for arbitrating access to a plurality of buses. In the preferred embodiment, a computer system is divided into a detachable laptop portion and an expansion base unit coupled through a shared PCI bus. Each of the two portions of the computer system includes separate PCI arbitration circuitry for arbitrating requests for the PCI bus from potential PCI and ISA bus masters. Included within the laptop portion of the computer system is a top level arbiter that determines whether the PCI arbiter in the laptop or expansion base unit has access to the PCI bus. Either PCI arbiter normally must receive a grant from the top level arbiter before it runs a cycle. While the laptop computer is docked, the top level arbiter selects between the PCI arbiters on an essentially time multiplexed basis. While the expansion base and laptop computer are undocked, the top level arbiter grants bus access to the laptop PCI arbiter.
Type:
Grant
Filed:
July 19, 1996
Date of Patent:
September 21, 1999
Assignee:
Compaq Computer Corporation
Inventors:
Dwight D. Riley, James R. Edwards, David J. Maguire
Abstract: Auto run apparatus, and an associated method, selectively permits execution of an auto run CD received at a CD ROM drive of a convergent device. When the auto run CD is received at the CD ROM drive, the operational mode of the convergent device is transferred to a computer mode. Thereafter, automatic execution of the CD is permitted.
Abstract: An apparatus and method for recovering "break" codes transmitted by a keyboard that are not properly received by the receiver of the computer system. The keyboard is an infrared keyboard that transmits to a receiver in the computer system "make" codes when the keys are depressed and transmits to the receiver "break" codes when the keys are released. Upon receipt of the "make" and "break" codes, the receiver keeps track of the status of each of the keys, i.e., depressed or released, by updating a database in response to receipt of the "make" and "break" codes. At select time intervals, the keyboard transmits to the receiver an "idle" code containing data corresponding to the status of each key. Upon receipt of the "idle" code, the receiver compares the "idle" code with the status of each key as indicated by the data base. The receiver then generates a "break" code for each of the keys that do not compare.
Abstract: A computer system with a plurality of devices compatible with the Fibre Channel Protocol, which computer system is provided with the capability to dynamically alter the configuration of the plurality of devices without a system reset, or without additional software overhead. This capability is realized by providing unique mapping relationships between low-level Fibre Channel information structures related to the devices and upper-level link elements compatible with an Operating System associated with the computer system.
Type:
Grant
Filed:
February 11, 1997
Date of Patent:
September 21, 1999
Assignee:
Compaq Computer Corporation
Inventors:
James F. McCarty, Richard D. Gunlock, Michael E. McGowen
Abstract: A computer system employing a bus protocol violation monitor system and method. The monitor system includes a bus wait timer logic circuit which comprises a state machine that receives a portion of the bus interface control signals, a programmable timer module and a plurality of data selectors that are actuatable responsive to a control input. In addition to storing the violation information in a register, the system provides for interrupts with graded levels of priorities.
Abstract: An apparatus, such as a computer, comprises a housing having an interior portion into which a printed circuit board may be inserted. The printed circuit board, when inserted, is supported by a support structure. A spring mechanism resiliently supports a heat sink structure in contact with a major side portion of the inserted printed circuit board. During operation, fluid flows in thermal transfer relationship with the heat sink structure. In this manner, heat is transferred from the heat sink structure to the fluid.
Type:
Grant
Filed:
May 11, 1998
Date of Patent:
September 14, 1999
Assignee:
Compaq Computer Corporation
Inventors:
Daniel N. Donahoe, Henry E. Mecredy, III
Abstract: A method of emulating a peripheral device in a multiprocessor computer system to test device driver programs. The emulation program is loaded by a host microprocessor into one or more of the other microprocessors (target microprocessors) which are not being accessed by the operating system software. After the emulation program is loaded, control vectors to the entry point of the emulation program, where the environment in each of the target microprocessors are initialized for the emulator program. If more than one target microprocessor are utilized, then one of the target microprocessors are designated as the "master" microprocessor, which accepts interprocessor interrupts from the host microprocessor. When the device driver program running on the host microprocessor invokes an I/O command, and emulation mode is selected, then an interprocessor interrupt (IPI) is asserted to the master microprocessor.
Abstract: A computer system incorporating a two-piece authentication procedure for securely providing user authentication over a network. In the disclosed embodiment of the invention, a user password is entered during a secure power-up procedure. The user password is encrypted by an external token or smart card that stores an encryption algorithm furnished with an encryption key that is unique or of limited production. A network password is thereby created. The network password is maintained in a secure memory space such as System Management Mode (SMM) memory. The network password is then encrypted and communicated over the network. The network password may be encrypted using the server's public key or another key that is known to the server. Optional node identification information is appended to the network password prior to communication over the network. Once received by the server, the encrypted network password is decrypted using the server's private key.
Abstract: A computer system having a processor is provided with a memory controller serially coupled to a serial-access programmable read-only-memory ROM (PROM) through a serial PROM interface of the controller. A random-access memory controller randomly accesses the BIOS code in the serial PROM during power-up of the computer system in response to read requests from the CPU. If the memory controller cannot immediately process the read requests from the CPU, the controller creates wait states for the CPU. An auto-configuring memory controller sequentially accesses the entire BIOS code in the serial PROM during power-up and prior to the running of the CPU and copies it to a portion of base memory, eliminating random accesses to the PROM.
Abstract: A SCSI cable including first and second SCSI cable segments, a SCSI Y connector that includes connector contacts to couple corresponding SCSI signal conductors of each of the SCSI cable segments together and to corresponding ones of the connector contacts of the SCSI Y connector, a first resistor coupled between the SCSI request signal conductor of each of the SCSI cable segments and a corresponding connector request signal contact of the SCSI Y connector, a SCSI end connector including connector contacts that couples corresponding SCSI signal conductors of the second SCSI cable segment to corresponding connector contacts, and a second resistor coupled between the SCSI request signal conductor of the second cable segment and a corresponding request signal contact of the SCSI end connector. In this manner, the request signal asserted by any one of the targets is effectively filtered to reduce or otherwise eliminate reflections on the SCSI request signal.
Abstract: A personal computer includes a flat panel or LCD display for displaying computer status information. The display includes an overlying transparent touchpad. When the touchpad is touched, appropriate signals are processed so that movements of the user's finger on the touchpad can be indicated by displaying altered images on the display that correspond to the movement of the user's finger. In this way, the user gets an immediate visual feedback through the LCD display of what changes can be or have been made by touchpad control.
Abstract: An adaptive networking device including a switch module having several ports and operable according to a first protocol and a repeater module also having several ports and operable according to a second protocol. The adaptive networking device preferably includes several connector ports for coupling to external data devices, such as computers, work stations, file servers, modems, printers, repeaters, switches, routers, hubs, concentrators, or the like, for establishing a networking system. Also, the adaptive networking device preferably includes an interface circuit for each connector port for detecting communication from a data device on the corresponding connector port and for coupling that data device to either the switch module or the repeater module. The interface circuit preferably senses the protocol of the communication and automatically couples the data device to the corresponding and compatible communication module.
Abstract: An apparatus controls a signal that indicates to a plug-in component board that it is to be connected to a 64-bit data path in a computer system. The apparatus comprises a timing circuit for receiving a reset signal and providing first and second complementary logical signals in response thereto. A selection switch receives the first and second logical signals as well as a control signal and outputs a third signal as determined by the logical level of the reset signal. A method involves generating first and second complementary signals from a reset signal, selecting between the first complementary signal and a control signal, and outputting a third signal, the logical value of the third signal being determined by the logical value of at least one of the reset signal and the control signal.
Type:
Grant
Filed:
June 5, 1998
Date of Patent:
September 7, 1999
Assignee:
Compaq Computer Corporation
Inventors:
David Heinrich, Robert Olson, Siamak Tavallaei
Abstract: A method for permitting access to secured computer resources based upon a two-piece user verification process. In one embodiment of the invention, the user verification process is carried out during a secure power-up procedure. At some point during the secure power-up procedure, the computer user is required to provide an external token or smart card that is coupled to the computer through specialized hardware. The token or smart card is used to store an encryption algorithm furnished with an encryption key that is unique or of limited production. The computer user is then required to enter a plain text user password. Once entered, the user password is encrypted using the encryption algorithm contained in the external token to create a peripheral password. The peripheral password is compared to a value stored in either secure system memory or in memory contained within a secured resource itself. If the two values match, access to the secured resource is permitted.