Abstract: A computer system includes a computer system unit and a power supply circuit. The power supply circuit is coupled to receive input power and generate output power. This circuit includes a circuit to generate a control signal that is related to the power level of the input power. The control signal has a first value relative to the input signal if the input signal exceeds a selected threshold level and the control signal has a second value relative to the input signal if the input signal does not exceed the selective threshold value. The power level of the output power is controlled so that it does not exceed a maximum power level which is based on the level of the control signal.

Abstract: An improved method and apparatus for creating a context-sensitive pathsend in a asynchronous data packet network of the kind used typically in on-line transaction processing where a particular receiving server in a server pool must communicate with a particular originating client. By piggybacking messages and employing run-time binding to create a logical connection between the server and client, the present invention achieves a dramatic improvement in processing data packets and minimizing system resources. In a preferred embodiment the invention is backwardly compatible with existing context-free applications.

Abstract: An electrostatic discharge protection system provides electrostatic discharge protection for an integrated circuit having a package and a semiconductor device installed within the package. The package includes a first pin, a second pin and a reference pin. The semiconductor device includes a first conductor that connects with the first pin, a second conductor that connects with the second pin, and a reference conductor that connects with the reference pin. The integrated circuit operates within one of a normal operating mode and a power conservation mode when the first and second pins receive a power supply signal. The electrostatic discharge protection system includes a first protection device that detects and couples electrostatic discharge events from the first conductor to the reference conductor by reference to a voltage potential difference between the second conductor and the reference conductor.

Abstract: A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. Contiguous virtual memory address space must be allocated for the AGP device within the addressable memory space of the computer system, typically 4 gigabytes using 32 bit addressing.

Abstract: An apparatus and method for performing remote financial transactions over an interactive network using a user operated payment module such as an initialized remote control device. The secure remote financial transaction system uses password security as well as a secure method for selecting and implementing personal passwords.

Abstract: A system for compressing and decompressing sequential records to store only those parts of a record which differ from the previous record. The system for compressing includes a bit map which indicates which parts of a record if any are the same as the preceding record. The system enables compression and decompression of records without the need to access additional blocks and perform additional disk I/Os to obtain the expanded version of a given compressed record.

Abstract: A first computer is capable of being used with a second computer. The second computer has a second bus and a second central processing unit that runs a second operating system that provides a user interface. The first computer includes a first bus for connection to the second bus. The first computer also has a first central processing unit configured to run a first operating system that provides a user interface and configured to cooperate sometimes with the second central processing unit such that the first and second computers operate with one of the central processing units as a single computer when the first and second buses are connected.

Abstract: A hardware/software system for analyzing memory dumps. The system collects data structures in a memory dump into logical tables, one logical table per selected type of data structure. The logical tables are generated by use of extraction logic for extracting data in data structures in the memory dump. The extraction logic is used in conjunction with a template library that contains data structure definitions for various types of data structures. The extraction logic, together with the template library, make possible populating logical tables with the contents of data structures found in the memory dump. Each row in a logical table is dedicated to one data structure of the selected type. Collecting data structures into logical tables makes available the power of a standard database management system for operating on the logical tables to determine the cause of a crash of a hardware/software system for which the memory dump was taken.

Abstract: Faults in a computer system having circuits are managed by fault detectors connected to detect fault states of respective circuits. A fault manager associates the fault states with the respective circuits. The fault manager includes a system manager connected to identify which of the circuits is causing faulty operation in the computer system. The fault detectors associated with the respective circuits are configured to detect faulty operation of and to generate fault state information for the respective circuits. A central manager is connected to accumulate fault state information from the fault detectors. One of the circuits includes a bus, and the fault state includes a bus error condition. The bus is connected to multiple devices, and the fault manager identifies which of the multiple devices causes the bus error condition. One of the circuits includes multiple modules, and the fault manager identifies fault states of the multiple modules. The modules include state machines.

Abstract: Stackable modules using infrared (IR) radiation for communication. Each module includes a housing with upper and lower holes and IR transceivers aligned with the holes. One of the two IR transceivers or transceiver sets detects IR communications through a lower hole and transmits through an upper hole, and the other detects IR communications through an upper hole and transmits through a lower hole. In this manner, the stackable module uses IR radiation to communicate with similar modules both above and below the module. The module further includes communication logic coupled to the transceivers to control communications between the transceivers of different modules. The module preferably includes a network device operating according to any desired network protocol. A stack network system includes a chassis with several slots, where one or more stackable modules are removably plugged into the slots of the chassis. Management may be distributed among the modules or centralized.

Abstract: The present invention enhances the robustness of the Plug-and-Play BIOS, and reduces the amount of ROM work required to support each product, by rearchitecting the static support, conflict resolution, and initialization of system board devices to combine such functionality into fewer software components having greater product independence.

Abstract: A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a memory page, and feature flags that may be used to customize the associated memory page.

Abstract: A questionless case-based knowledge base suitable for access by an intelligent search engine and an associated method for constructing the same from pre-existing on-line documentation. A case structure for questionless cases is determined. The determined case structure includes a first field for containing a title for a case, a second field for containing a description of the case and a third field for containing a solution for the case. On-line documentation having information directed to a plurality of topics, each of which includes a title portion and a contents portion, is then provided. The information directed to each of the plurality of topics is then reconfigured into the determined case structure such that the title portion of each topic is configured as a first field of a corresponding case and the contents portion of each topic is configured as a second field of the corresponding case.

Abstract: Representatively using force sensing resistors as key switch elements, keys on a computer keyboard are each provided with pluralities of different keystroke output function signals which may be selectively varied in response to simply altering the user keystroke force imposed on the key. In addition to being provided with a default key force range/output signal correlation, the keyboard may be programmed by the user to customize the key depression force ranges associated with selected different keystroke output signals. Representatively illustrated additional uses of this key force/output signal correlation capability include a key force-based typing correction mode and a combination character and key force sequence-based user password access system. To further expand the individual key functionality of the keyboard, a combination of sensed key depression force and duration is used to generate an additional keystroke output function signal for a given key.

Abstract: A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in memory, and feature flags that may be used to customize the associated page. One of the feature flags is used as a Present Bit for a corresponding memory page.

Abstract: A routable operand and selectable operation processor multimedia extension unit is employed to motion compensate MPEG video using improved vector processing. A vector processing unit executes an add and divide instruction that adds two vector registers and divides the result in a single instruction. This is implemented through loading a first vector register with a first plurality of elements from a source block. A second vector register is then loaded with a second plurality of elements that are adjacent to the first plurality of elements. The add and divide instruction is then executed on the first and second vector registers, yielding an interpolated source element that is stored in a resultant vector register.

Abstract: A computer system includes a CPU and a memory device coupled through a North bridge logic device. The computer also includes a South bridge logic device coupled to the North bridge by a primary bus. The South bridge waits as long as possible before asserting a flush request (FLUSHREQ) control signal to the North bridge. The South bridge asserts the FLUSHREQ signal to the North bridge after a peripheral device coupled to the South bridge requests access to the primary bus to run a cycle. The South bridge first flushes a write queue before asserting the FLUSHREQ signal to the North bridge. In response to the FLUSHREQ control signal, the North bridge flushes one or more of its own internal write queues in preparation for the upcoming peripheral device cycle.

Abstract: A computer system includes a touchpad with one or more overlays providing the computer system with various input control functions. The overlay preferably includes tactile response elements to provide tactile feedback to the operator as an indication that a portion of the overlay has been pressed. The touchpad includes a capacitive sensor. Electronics coupled to the touchpad determine which portion of the touchpad sensor surface area has been touched or pressed. The amount of tactile feedback to the computer operator can be varied through the design and construction of the overlay and the overlay may be provided with no tactile feedback, if desired. As such, numerous overlays can be placed on the touchpad of the computer system, thereby providing the computer system with multiple different input control functions. The computer operator may manually input the type of overlay being used into the computer.

Abstract: A system and process for power conservation in a portable computer system. When the application or hardware in use allows for reduced video performance, the refresh rate of the video graphics controller is reduced to a level which allows practical use of the display but consumes much less power than a normal mode.