Abstract: A cache system for multiple processors including multiple caches, one of the caches serving each respective processor, a main memory system, and a bus interconnecting the caches and the main memory, the bus allowing data to be written directly between the caches without accessing the main memory system.

Abstract: A sealed rechargeable lithium-ion battery pack which includes a switching voltage regulator. The regulator uses the normal cutoff transistors as the switching devices, and also includes a discrete inductor in the battery pack. The regulator is operated with programmable voltage and current parameters, under control of a microcontroller which is also inside the sealed battery pack enclosure.

Abstract: A fault tolerant 64-bit data-width peripheral component interconnect (PCI) bus system in a computer system that may recover from a fault(s) occurring on either the upper or lower 32-bit portions of a 64-bit data-width PCI bus. When a parity error is detected on one of either the upper or lower 32-bit portions of the 64-bit data-width PCI bus, the 32-bit portion not having the parity error is used to transfer data and the one having the parity error is inhibited from further use. The PCI bus may be dynamically configured for transfer of data at 64-bits per clock, or at 32-bits per clock over either the upper or lower portions of the PCI bus. New signals SWAP# and SWAP.sub.-- ACK# are used to accomplish the fault tolerant operation. 64-bit disable and swap enable bits in a PCI device command register are used to disable 64-bit data transfer, and swap data transfer from the lower portion to the upper portion of the PCI bus, respectively.

Abstract: Double buffering operations to reduce host bus hold times when an expansion bus master is accessing the main memory on a host bus of a computer system. A system data buffer coupled between the main memory and the expansion bus includes 256-bit double read and write buffers. A memory controller coupled to the double read and write buffers and to the expansion bus includes primary and secondary address latches corresponding to the double buffers. The memory controller detects access to the main memory, compares the expansion bus address with the primary and secondary addresses and controls the double read and write buffers and the primary and secondary address latches accordingly. During write operations, data to be written to the same line of memory is written to a first of the double write buffers until a write occurs to an address to a different line before data is transferred to main memory.

Abstract: In a computer system, an improved tool and method for debugging complex computer programs displays the relationship between processes and resources of the processes. Double clicking on the displayed information causes more detailed information to be displayed. The display is updated when predetermined operations are performed during debug. Debug commands are accepted by the tool through a graphical user interface using operations performed by the user directly on the graphical representation of program functions. The ability of the tool to accept user commands through the graphical user interface and to display critical debugging information using this same interface greatly facilitates program debugging.

Abstract: A computer system with a plurality of devices compatible with the Fibre Channel Protocol, wherein at least two of which devices are initiators. The computer system is provided with the capability to control and manage multiple initiators configured in an Arbitrated Loop. This capability is realized by manipulating the contents in outstanding.sub.-- link.sub.-- services arrays associated with the initiators.

Abstract: A computer convergence device, operable in a computer mode and, for example, a television mode, includes a computer, a display monitor for displaying images in both the computer mode and the television mode, and multiple video inputs for receiving various types of video signals, each being selectable during operation in television mode. A controller device is coupled to the computer for independently controlling and storing user selected video geometry settings for both the computer mode and the television mode, and further for independently controlling and storing user selected video quality settings for the computer mode, and each of the various video inputs.

Abstract: In a computer server orthogonally coupled processor and expansion circuit boards are respectively supported on corresponding vertical and horizontal chassis walls of the server. Upper and lower leveraged disconnect structures are respectively associated with the expansion and processor boards and are operative to disconnect either circuit board from the other circuit board without (1) disturbing the other circuit board, (2) using tools of any sort, or (3) damaging the mating circuit board connectors. The lower leveraged disconnect structure is also operative to recouple the disconnected processor circuit board to the undisturbed expansion circuit board.

Abstract: A computer system has a connector and a circuit card that is inserted in the connector. A mechanism that is associated with the connector and the card has a state for indicating when the card is secured to the connector. A controller of the computer system is configured to monitor the state and provide an indication when the state changes. A processor of the computer system is configured to determine when software of the computer system is interacting with the connector and based on the determining and the indication, regulating interaction of the computer system with the card.

Abstract: A DVD assembly, and an associated method, for a convergent device, such as a television converged into a computer. The DVD assembly is integrated into the convergent device to facilitate ease of user control over operation of the DVD assembly. Common control interfaces which include the "look and feel" of the control interfaces otherwise used by the convergent device simplify operational control over operation of the DVD assembly.

Abstract: The present invention provides a method and apparatus for re-assigning network addresses to a plurality of network servers by re-configuring a client host coupled to the network servers. According to the invention, when there are changes to network connections, the IP addresses (i.e., network addresses) of the individual network servers can be re-assigned automatically at the client host without powering off the network servers. According to the invention, in re-assigning a new network address to a port of the network server, a bootstrap protocol (BOOTP) request is first issued by the client host to the network server. The BOOTP request is received by the network server which then sends a BOOTP response to the client host to request a new network address. After the client host receives the BOOTP response, it sends a BOOTP reply to the network server. The BOOTP reply includes a new network address for the port of the network server. The above procedure is repeated for each port of the network server.

Abstract: The original firmware of a computing device is stored in a fixed non-volatile ROM-type memory while any subsequently issued replacement firmware correcting or upgrading erroneous firmware contained within the original firmware is stored in a reprogrammable EEPROM-type non-volatile memory. The locations in the fixed and reprogrammable memories storing the corresponding erroneous and replacement firmware, respectively, are identified in a data table that is also stored in the reprogrammable memory. A field programmable gate array connected to the reprogrammable memory uses the data table to identify computing device requests to the fixed memory for erroneous firmware and in response thereto inhibit output of erroneous firmware. The gate array further uses the data table to access the reprogrammable memory and output corresponding replacement firmware in substitution for the device requested original, but erroneous, firmware.

Abstract: A method of determining an object's position and associated apparatus provides positional information in a form that may be conveniently communicated to a computer system to calculate the object's position. In a disclosed embodiment, representatively incorporated in a computer keyboard, a method of determining an object's position includes forming an optical grid of overlapping beacons and detecting reflections of the beacons produced by the object when it intersects the grid. The disclosed embodiment utilizes two focused beacons to produce the optical grid.

Abstract: The present invention includes an event detector for detecting selected events occurring in a computer system which are programmed to automatically move a cursor image from a viewing area of a video display to an overscanned area of a video display. The invention further includes a cursor controller for generating the cursor image and controlling movement of the cursor image on the video display. The cursor controller automatically places the cursor image in the overscanned area of a video display when the event detector detects the occurrence of a selected event. Alternatively, the event detector can include a timer for delaying the notification of detection to the cursor controller of the selected event.

Abstract: A computer system is capable of playing audio CDs in a CD-ROM drive independent of the operating system by using an embedded CD-ROM drive application or a CD-ROM drive controller. When an audio CD mode switch of the computer system is in an "on" state and the main power switch of the computer is in an "off" state, the computer system is in an audio CD mode. When the computer is placed in such an audio CD mode, the computer either loads the embedded CD application from a non-volatile memory region such as read-only-memory (ROM) region or enables the CD-ROM drive controller of the CD-ROM drive to receive a CD selection and transmit the selections to the CD-ROM drive.

Abstract: An apparatus and a method perform an N-point Fast Fourier Transform (FFT) on first and second arrays having real and imaginary input values using a processor with a multimedia extension unit (MEU), wherein N is a power of two. The invention repetitively sub-divides the N-point Fourier Transform into N/2-point Fourier Transforms until only a 2-point Fourier Transform remains. Next, it vector processes the 2-point Fourier Transform using the MEU and cumulates the results of the 2-point Fourier Transforms from each of the sub-divided N/2 Fourier Transforms to generate the result of the N-point Fourier Transform.

Abstract: A hub circuit with an integrated bridge circuit carried out in software including a switch for bypassing the bridge process such that the two bridged networks effectively become one network. An in-band management process in software is disclosed which receives and executes network management commands received as data packets from the LANs coupled to the integrated hub/bridge. Also, hardware and software to implement an isolate mode where data packets which would ordinarily be transferred by the bridge process are not transferred except in-band management packets are transferred to the in-band management process regardless of which network from which they arrived. Also disclosed, a packet switching machine having shared high-speed memory with multiple ports, one port coupled to a plurality of LAN controller chips coupled to individual LAN segments and an Ethernet microprocessor that sets up and manages a receive buffer for storing received packets and transferring pointers thereto to a main processor.

Abstract: In a computer system, an improved tool and method for debugging complex computer programs is disclosed. The tool extracts critical debugging information from computer memory and/or remote storage memory and uses this information to graphically depict call relationships among various functions comprising the program which is the subject of the debugging operation. Debug commands are accepted by the tool through a graphical user interface using operations performed by the user directly on the graphical representation of program functions. The ability of the tool to accept user commands through the graphical user interface and to display critical debugging information using this same interface greatly facilitates program debugging.

Abstract: A computer system having a CPU, a disk array system accessible by the CPU, and a disk array controller that includes error detection and connection logic. The disk array controller includes a processor and a memory system connected to signal lines carrying data bits, address bits, and check bits. An error detection and correction device is connected to detect and correct N-bit errors in the data bits using the check bits, N being greater than two. An error in the address bits is detected using the same check bits. The data bits are organized as multiple bytes, and the error detection and correction device is connected to detect and correct up to eight-bit errors in each byte and to detect a single-bit error or a two-adjacent-bit error in the address bits.

Abstract: An improved method and apparatus for creating a context-sensitive pathsend in a asynchronous data packet network of the kind used typically in on-line transaction processing where a particular receiving server in a server pool must communicate with a particular originating client. By piggybacking messages and employing run-time binding to create a logical connection between the server and client, the present invention achieves a dramatic improvement in processing data packets and minimizing system resources. In a preferred embodiment the invention is backwardly compatible with existing context-free applications.