Abstract: In a diagnostic application, a plurality of independent test modules are executed in a multi-tasking fashion. The diagnostic application is modular with a front end module issuing commands to lower level modules. A lower level test dispatcher module receives information from the plurality of test modules pertaining to test parameters, including whether the test module is multitaskable. A test dispatcher controls the launching of the test modules according to the test parameters. A test definition tool is provided to graphically develop test scripts by moving icons from one list to another. The output of the test definition tool is a scripting language readable by the diagnostic application.

Abstract: The invention is a computer system with a button array on the computer chassis for simulating the operation of common consumer electronic devices. Each button of the array of buttons is hardwired to the system processor. Upon activation of one of these buttons, an interrupt signal is sent to the system processor. The system processor halts whatever it is doing, and subsequently identifies the activated button. A signal generator attached to the buttons then sends the system processor a second interrupt signal, such that upon exiting the handling of the first interrupt, the system processor is presented with a second interrupt. The system processor then handles the second interrupt. While handling this second interrupt, the system processor executes whatever function corresponds to the activated button. The system processor then exits the handling of the second interrupt and resumes whatever activity it was engaged in before the activation of the button.

Abstract: A method for controlling flow, through a computer hardware resource, of information to and from computer applications. When a flow of information is initiated from one of the applications, a determination is made whether the resource is being accessed by another one of the applications and, if so, the flow of information from the first application is delayed. If not, then the flow of information is enabled. When a flow of information is initiated toward the applications, a determination is made to which one of the applications the information is flowing, and the flow is directed to that one application. A graphical interface associates, in the mind of a user, a computer hardware resource with a corresponding real office device, the computer resource enabling the computer to function like the consumer device.

Abstract: A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as an AGP graphics controller, and a host processor and computer system memory wherein AGP transaction read requests are merged from the AGP graphics controller and retired when these requests are within a cacheline of the memory being accessed. The core logic chipset will request a memory cacheline read as it begins processing a current AGP transaction read request. Once the memory read access is initiated, the transaction read request will be popped off an AGP request queue in order to evaluate the next in order transaction request. If the next request can be partially or completely retired by the memory read access previously started, then the memory access that would have been normally required may be skipped and the data from the previous memory read access is used instead.

Abstract: The present invention relates to the placement of signal traces on a two-sided printed circuit board such that impedance of the traces is controlled and so that the number of power and ground pins required on an integrated circuit are minimized.

Abstract: A computer system has a housing and a central processing unit located inside the housing. The computer system also has a peripheral unit mounted in and removable from the housing and a communication port connector exposed on the outside of the housing for connection of and communication with external devices. The computer system has a dedicated communication link in the housing for communication with the peripheral unit. The computer system also has a device for connecting the peripheral unit to the port connector when the peripheral unit is removed from the housing and circuitry for coupling the dedicated communications link to the port connector when the peripheral unit is connected to the communication port connector. The computer system has a device for holding a portable disk drive constructed for insertion into an internal drive bay of a computer unit having a shell for covering and protecting the disk drive.

Abstract: Apparatus, and an associated method, for requesting initiation of generation of an interrupt at an I/O APIC (input/output advanced programmable interrupt controller) of a multi-processor computer system. Initiation of generation of the inter-processor interrupt is requested by a peripheral component device, such as a PCI bus controller, not directly connected to an APIC bus extending to interrupt controllers associated with each of the processors of the multi-processor computer system. The interrupt permitted to be initiated by the peripheral component device includes, inter alia, a remote read request.

Abstract: A computer system having an interconnection apparatus for connecting processors, peripherals and memories, the system including a plurality of electronic devices, and a multiple long bus structure with impedance elements disposed thereon for providing non-terminal termination points.

Abstract: A PCI bridge is configured to perform delayed read operations in response to a memory read initiated on the PCI bus. Normally, the PCI bridge is configured to discard delayed read data read from main memory following a predetermined discard count time after the PCI master establishing the delayed read operation is retried on the PCI bus. The computer system further includes a secondary bus bridge such as an ISA bridge for providing an interface between the PCI bus and an ISA bus. When an ISA device desires to read data from the main memory, the ISA bridge asserts a flush request signal. The PCI bridge responsively flushes any pending CPU to PCI transactions pending within the PCI bridge. When the flushing operation is complete, the PCI bridge asserts an acknowledge signal. A PCI arbiter for arbitrating ownership of the PCI bus may increase a level of arbitration priority provided to the ISA bridge in response to assertion of the acknowledge signal.

Abstract: A bridge circuit for coupling a first bus to a second bus includes a read buffer adapted to store read data and control logic. At least a portion of the read data includes prefetch data, and the read data is associated with a requesting device coupled to one of the first and second buses. The control logic is adapted to identify a write request having a target address on one of the first and second buses, flush at least a portion of the prefetch data in response to the target address corresponding to the requesting device, and transfer the write request to the requesting device independent of the read buffer. The write request is useful for signaling the requesting device that the read data is no longer required.

Abstract: The cage-supported hard disk drives in a computer server system are coupled to connectors on the cage back plane circuit boards and are controlled by a pair of array controller cards which are hot-plug connected in a redundant manner on the system I/O board using a pair of connectors mounted on the I/O board, each connector having first and second sets of electrical contacts thereon. Connector edge portions of the array controller cards are plugged into the I/O board connectors and have first and second sets of electrical contacts that engage the corresponding first and second sets of electrical contacts on their associated I/O board connectors.

Abstract: A computer server unit has a closely spaced series of parallel, facing processor modules with inner edge portions thereof being operatively and removably received in socket connectors on a main system board within the server unit housing. Voltage regulation modules, in the form of power converter cards, are interdigitated with the series of processor modules, with each power converter card being operatively coupled to an associated one of the processor modules. To permit the efficient dissipation of operating heat from the closely spaced processor modules and voltage regulation modules, each removable processor module has a specially designed cooling module supported thereon for removal therewith from the system board.

Abstract: Power is managed in a computer system that includes a power-using device. The power used by the device is regulated based on a measured rate of communications with the device.

Abstract: A printed circuit board or card includes a pair of ball grid array packages connected one over the other on opposite sides of the board or card. The packages may connect through feed-through vias so that board space on the underside of the board, populated by feed-through vias, can be utilized to provide additional functionality. In one implementation, GTL resistive terminations and decoupling capacitors may be included in the ball grid array package on the underside of the board or card.

Abstract: A self-contained liquid cooled heat sink system disposed in a computer has a plurality of socket portions through which a cooling liquid is pumped. Operating heat from a plurality of heat-generating computer components, representatively circuit board-mounted processor chips, is efficiently transferred to the heat sink system by heat pipe modules associated with the heat-generating components. Each module includes (1) an evaporator plate held in thermal contact with its associated component, (2) a condenser plate removably plugged into one of the sockets and in a heat transfer relationship therewith, and (3) a plurality of thermosyphoning type heat pipes interconnected between the evaporator and condenser plates. The use of the heat pipe modules permits rapid and easy pull-away electrical and cooling system disconnection for each processor board as well as providing for effective cooling of the processors without the necessity of forcing a flow of air across them.

Abstract: A method and apparatus for decoupling input/output (I/O) from host processing through main memory. A command packet architecture and distributed burst engine for communicating data to an I/O device without using memory mapped I/O or host processor synchronization. The packet architecture includes a header having fields for linking packets in a list with physical and virtual addresses, thereby eliminating address translations. The distributed burst engine includes buffers and controllers for bursting the linked lists of packets between main memory and the I/O device. Doorbell registers are included for the host processor to indicate to the DBE that an event has occurred. The distributed burst engine is versatile enough to be bus independent and located virtually anywhere between main memory and the I/O device.

Abstract: In a color sequential system using LCDs, the LCD must operate faster than the frame rate because red, green, and blue are done sequentially. Ferroelectric LCDs can do this, but they are not analog devices and so cannot provide analog display levels. Instead, a pulse width modulation (PWM) technique is used. In the system of the present invention, each pixel has three storage devices to hold RGB analog levels. A latch is used to load these values in parallel. Then an analog 3:1 multiplexer is used to select the proper storage device for the current sequential color. The multiplexer output goes to a comparator, which has a sawtooth waveform input at much faster than the frame rate. The comparator output changes with the sawtooth level, so that PWM control is provided for each pixel. As an alternative, standard analog LCD pixels can be sequentially switched between three color input storage devices.

Abstract: A computer system includes a processor bus having processor data and processor check bits for performing error detection and correction of the processor data. A CPU is coupled to the processor bus. A memory sub-system is coupled to the processor bus and includes memory check bits, memory address bits, and memory data bits, and an error detection and correction device for detecting an error in the memory address bits using the memory check bits and for detecting an error in the memory data bits using the memory check bits. The CPU can include a processor from the Pentium.RTM. Pro family of processors. The error detection and correction device generates a syndrome table which includes a plurality of entries mapped to correctable or uncorrectable errors, in which a detected multiple-bit error in the memory data bits is mapped to an uncorrectable error entry and a detected error in the memory address bits is mapped to an uncorrectable error entry.

Abstract: A fast boot computer which has three user-selectable modes of performing POST operations. The user can select full POST or quick POST be performed, as in conventional computers. However, he can also select an intermediate mode, wherein the full POST is performed if and only if a given number of days (as programmed by the user) have elapsed since the last full POST operation. This permits users to set their own trade-off between fast boot operation and maximum reliability.

Abstract: An apparatus is provided for coupling a printed circuit board within a printed circuit board cage. The apparatus includes a first portion coupled to the printed circuit board cage. A second portion is rotatably coupled to the printed circuit board, and includes a cam surface formed on a first end portion thereof. The cam surface is engageable with an interior surface of a bore in the first portion to urge the second portion and the printed circuit board from a first position to a second position. The second portion also includes a latch formed on a second end portion thereof. The latch is engageable with a corresponding latch on the printed circuit board in response to the second portion being located in the second position.