Abstract: A system is provided for scanning batch-type documents containing indicia on either a single side or on two sides of each document sheet. Misfeeds through a scanning device are identified by comparison of an anticipated number of pages with an actual number of scanned pages. Similar misfeeds may be identified by comparison of first and second series of pages in two-sided documents. Automatic collating of scanned pages is then performed where desired. The automatic collating may be based upon simple interleaving of pages, or upon recognition of page identifiers, such as page numbers in common or anticipated regions of the page. The scanning, analysis and collating operations may be followed by other processing steps, including transmission of facsimiles, printing, copying, and so forth.

Abstract: A software program is used in conjunction with a standard general purpose single or multi-processor computer system as a means of implementing an I2O-compliant input-output processor (“IOP”) without requiring a special hardware IOP processor embedded on a PCI device card and connected to a computer system PCI bus. Software modules are inserted into the operating system during computer system initialization, thereby causing the I2O software operating system to operate as if it is communicating with a physical IOP installed on a PCI bus, but instead is utilizing at least one of the multi-processors of the computer system. These software modules intercept messages to and from software device driver modules and assign them to the V-IOP, thus making operation of the computer system indistinguishable from messages that would have been processed by a hardware implemented IOP in a computer system.

Abstract: A computer system having a main memory and a cache memory, the computer system uses portions of the cache memory to store information from defective main memory locations until the main memory can be repaired. The address space of the main memory is always maintained by substituting cache-lines of cache memory for the defective main memory locations. A fail-over memory status bit in the cache memory controller indicates when a cache line of the cache memory contains fail-over information from the defective or failing main memory so that that cache-line will not be written over by a cache replacement algorithm. When the fail-over status bit is set, the contents of the fail-over memory location(s) remains in the cache-line and all memory reads and writes are directed to only that cache-line of the cache memory and not the main memory for the fail-over memory location(s).

Abstract: A computer system that includes a system ROM with at least two sets of character strings, one set in English and at least one other set in a non-English language. Generally, each set of character strings includes characters, words and phrases that are translations of corresponding character strings in the other sets. In a preferred embodiment, the system ROM includes only two sets of character strings—one English and the other non-English. The non-English set of character strings is included as part of a “language module” stored or flashed into the system ROM. The character strings preferably are used to provide information and instructions to a user during system setup. When setup is run, the computer system determines whether a valid international language module is included in the system ROM. If a valid language module is included, the user is prompted to select either English or whatever international language is provided in the language module.

Abstract: A storage device capable of performing diagnostics tests on itself to render an opinion of its health to a host computer is disclosed. Test commands are received over an industry-standard interface. The tests may be run in off-line or captive modes. Off-line tests are subject to interruption from the host computer whereas captive tests are not. Unless a command is received that instructs the storage device to stop testing or power-down, the storage device suspends the test, executes the host command and resumes testing. Power management is disabled while the tests are run to prevent the storage device from inadvertently powering down. A number of specific tests may be performed, including a general quick test and a comprehensive test. Failures detected during the tests are logged in a non-volatile memory of the storage device and include an indication of which component failed and at which point in the test that component failed.

Abstract: A clock distribution system for a semiconductor device provides for both on-chip and in-package clock distribution via on-chip and in-package clock distribution networks. Each of these networks is selectively enabled depending on the mode of operation. Specifically, for wafer testing, the on-chip clock distribution network is selected. Thus, a probe tester need only provide a single clock source with conventional timing specifications to test the operation of the chip. In contrast, during normal operation, an in-package clock distribution network is enabled. In-package clock routing provides the lowest variation mode and thus, will result in the maximum clock frequency for the chip.

Abstract: A method and system of intrachassis computer component command and control. The existing power rail is used as network connectivity. Further, the CEBus standard (or a CEBus standard modified for the particular power bus) is used to provide platform management functionality. This management functionality is similar to that provided by the proposed IPMI specification. However, the management functionality is implemented intrachassis, that is, it is applied to the internal components of the machine. Particularly advantageous functions, such as rollcall enumeration and command authentication and verification, are included in a preferred embodiment. Further, because these innovative techniques utilize the existing power rail, no additional external cables are required.

Abstract: A method and apparatus are provided for ensuring that a clocked circuit will function after fabrication, regardless of the presence of clock skew. More particularly, a method and apparatus are shown for de-skewing the clock signals of such a clocked circuit only when clock skew is present. When such clock skew does not develop, peak performance of the associated circuit can be achieved by turning off the de-skewing function without removing that functionality from the circuit.

Abstract: A processor-based system includes a processing unit. The processing unit includes at least a processor and preferably also a cache memory, a cache memory controller and a numerical coprocessor. The processing unit is reset in response to a system reset signal being asserted at a reset input node and only selected portions of the processing unit are reset in response to a partial-reset signal being asserted at a partial-reset input node. The system can also include a number of other components such as video circuitry, a hard disk drive, bus interface circuitry, a speaker, a keyboard controller and a keyboard.

Abstract: A battery casing is adapted to fit into at least two different receiving bays of different sizes. The casing includes an adapter panel which is movable into at least two positions. Moving the adapter panel to the first position increases the effective width of the casing, and allows the battery to be inserted securely into a first receiving bay. Moving the adapter panel to the second position maintains the original width of the casing. This allows the battery casing to be inserted securely into a receiving bay, which has the same width as that of the original casing.

Abstract: An identification system for a processor-based device. The identification system is readily utilized with rack-mounted devices, such as servers. The system includes an actuator, such as a pair of pushbuttons located at the front and the rear of the device. The system also includes an indicator, such as a pair of lights at the front and the rear of the device that are illuminated upon actuation of the actuator. Thus, a clear indicator is visible from the front and from the rear of the device to permit service or replacement without inadvertent disconnection of an adjacent device.

Abstract: A data signal attenuator is constructed to include an optocoupler, a biasing source for powering the optocoupler and restoring the amplitude of an originally transmitted signal, and a connector for connecting the attenuator to the exterior of a receiving device. When connected to the receiver, the attenuator electrically connects a single-ended data transmission line to the receiving device. The external connection of the attenuator to the receiving device thus enables existing receivers to have the benefits of an optocoupler based attenuator without the necessity of redesign.

Abstract: A computer system implementing a fault detection and isolation technique tracks failed physical devices by error codes embedded in various component in the computer system. The computer system comprises one or more CPU's, one or more memory modules, a master control device, such as an I2C master, and a North bridge logic device coupling together the CPU's, memory modules, and master control device. The master control device also connects to the CPU's and memory modules over a serial bus, such as an I2C bus. Each component includes a nonvolatile memory coupled to the I2C bus for storing error information. If a component fails, a CPU stores an error code into the nonvolatile memory via the I2C bus. During initialization, the CPU creates a logical resource map which includes a list of logical addresses of all available (i.e., fully functional) devices.

Abstract: Load/store execution order violations in an out-of-order processor are reduced by determining whether a source address of a load instruction is the same as a destination address of a store instruction on which execution the load instruction depends. If they are the same, then execution of the load instruction is delayed until execution of the store instruction. In an system where virtual registers are mapped to a physical register, the physical registers mapped by the store and load instructions are compared. A table has entries corresponding to instructions in an instruction queue. In each table entry corresponding to a store instruction, the store instruction's destination address offset and physical register reference are saved. A load instruction's source address offset and physical reference are compared with each of the table entries corresponding to store instructions to determine whether a dependency exists.

Abstract: An apparatus for identifying memory requests originating on remote I/O devices as non-cacheable in a computer system with multiple processors includes a main memory, memory cache, processor, cache coherence directory and cache coherence controller all coupled to a host bridge unit (North bridge). The I/O device transmits requests for data to an I/O bridge unit. The I/O bridge unit forwards the request for data to the host bridge unit and asserts a sideband signal to the host bridge unit if the request is for non-cacheable data. The sideband signal informs the host bridge unit that the memory request is for non-cacheable data and that the cache coherence controller does not need to perform a cache coherence directory lookup. For cacheable data, the cache coherence controller performs a cache coherence directory lookup to maintain the coherence of data stored in a plurality of processor caches in the computer system.

Abstract: A system and method to facilitate the connection or removal of a first connector from a second connector located on a side of a device having an obstructed view. The system includes a device having a map illustrating the portion of the device that is obstructed from view. The map is located on a more visually accessible portion of the device. The method includes using the map to identify the location of a first connector on a device. The device is then coupled to a system or second device by connecting or removing a second connector, such as an electrical cable or water hose, from the first connector.

Abstract: A system and method for effectuating distributed consensus among members of a processor set in a multiprocessor computing system that is effective even when only a single surviving processor is operational and is achieved through joint implementation of a virtual state machine utilizing a sequence of numbered input commands. System synchronization is achieved by having all of the processors agree on the sequence of input commands so that they execute the same virtual state machine. Input commands are numbered consecutively and the processors use a set of shared stores (e.g. disk drives) to communicate amongst themselves requests (i.e. ballots) for new state machine inputs (or commands) and state machine inputs that have already been chosen (i.e. committed commands). A consensus process is used to decide upon (or commit) each command and this consensus is achieved using a majority of known system stores rather than a majority of known processors.

Abstract: A laptop computer system executes automatic battery calibration to improve the accuracy of the battery's internal charge monitor. The calibration procedure drains the battery to approximately 0% of charge capacity during normal computer operation, permitting a user to operate the computer without risking power failure when the battery discharges. The computer returns to normal operation if either the AC power or the battery is removed. During the calibration procedure, the computer system prevents power management software from forcing shut down before the battery completely drains.

Abstract: A computer system having a highly parallel system architecture with multiple central processing units, multiple core logic chipsets and pooled system memory is provided with one or more AGP ports capable of connection to AGP devices. A memory manager is provided within the operating system for allocating pooled memory resources without regard to the location of that memory. A method is presented for dynamically allocating memory for the AGP device that is located on the same core logic chipset to which the AGP device is connected. By allocating local memory instead of allocating memory on remote core logic units, the AGP device can access the needed memory quickly without memory transmissions along the host bus, thereby increasing overall performance of the computer system.

Abstract: The invention provides computer apparatus for performing a square root or division operation generating a root or quotient. A partial remainder is stored in radix-2 or radix-4 signed digit format. A decoder is provided for computing a root or quotient digit, and a correction term dependent on a number of the most significant digits of the partial remainder. An adder is provided for computing the sum of the signed digit partial remainder and the correction term in binary format, and providing the result in signed digit format. The adder computes a carry out independent of a carry in bit and a sum dependent on a Carry_in bit providing a fast adder independent of carry propagate delays. The scaler performs a multiplication by two of the result output from the adder in signed digit format to provide a signed digit next partial remainder.