Abstract: A computer system having integrated remote console functionality. Cycles intended for a video graphics controller are snooped to acquire the video data or control information contained in the cycle. Analysis is performed on the video data to detect sequential or repetitive operations. The video data is encoded into higher level primitives, if possible. The video data and primitives are held in a first-in-first-out (FIFO) memory until the FIFO reaches a critical level, or a staleness timer times out. Special firmware executed in system management mode reads the FIFO and converts the video data and primitives into conventional ASCII text or the required format. The firmware also maintains a copy of the video frame buffer to further encode the video data, if possible. The firmware then transmits the conventional ASCII text via a modem to a user stationed at a remote computer system.

Abstract: A media meter mounts to a surface of a removable storage media or other product, and provides a visual indication of one or more parameters of the storage media or other product. The media meter includes circuitry that detects status signals transmitted by rf transmissions or directly connected by wires between an auxiliary memory device mounted on the storage media or product, or receives status signals via rf transmissions directly from the auxiliary memory. As another alternative, the media meter may be integrated with the auxiliary memory to receive status signals directly from the auxiliary memory. The status signals indicate the capacity of the storage media, the number of read and/or write errors that have occurred during back-up and retrieval, the number of times the storage media has been loaded with data or other information, and other dynamically-varying parameters.

Abstract: A multi-ported SRAM memory cell includes a pair of inverters that holds the data bit. The state terminals of the memory cell connect via a separate read and write data path to the bit lines. The read bit lines connect to a pull-down transistor stack. The first transistor in the stack is gated by the word line, and the second transistor is gated by the state terminal of the memory cell. If the word line is asserted and the second transistor is turned on by the state of the memory cell, the bit line is connected to ground, thus pulling the bit line low. Conversely, if the second transmitter is not turned on, the bit line stays at a high voltage level. In a preferred embodiment, the memory cell is isolated from the pull-down transistor stack by an isolation buffer, such as an inverter, which inverts the voltage on the state terminal of the memory cell.

Abstract: A method for detecting an image edge within a dithered image. A pixel within a support region is selected for processing. The differences between pixel values in the region and the selected pixel are computed to form a current difference map. Whether the selected pixel in the region differ by no more than one resolution level from any other pixel of the region is determined from the current difference map. An edge is determined not to exist within the region if the difference map for a region contains no values differing by more than one resolution level. An edge is determined to exist within a region if the difference map for the selected pixel and region contain values differing by more than one resolution level. Alternatively, a difference map for the selected region of support is determined and compared to a table of all possible valid difference maps. If a corresponding difference map is found within the table then an edge does not exist within the presently processed region of support.

Abstract: An in-band/out-of-band alert delivery system for a computer system manager includes an alert log which maintains a record of alerts to be delivered and the status of those alerts, an alert manager for making a first attempt to deliver each alert, and a retry manager for making subsequent attempts to deliver alerts as becomes necessary and appropriate. The alert delivery system may also include a bus master interface manager for making in-band alert deliveries and a communications manager for making out-of-band alert deliveries. Telephone numbers are provided to the communications manager by an alert destination list. Out-of-band alert deliveries may be made via a modem, a universal asynchronous receiver transmitter, or the like.

Abstract: The present invention relates to a method and apparatus for determining capacitance and charge models for MOS devices to be used in calculating delays in a timing verifier for a circuit. The models are generated by first creating a variety of configurations of MOS devices which vary the inputs to the source, drain, and gate. Such inputs may include rising and falling values as well as constant values at VDD and VSS. Simulations are run on all of the configurations using conditions anticipated for the circuit to be analyzed. Capacitance values obtained from the simulations are used to determine models based upon length and width of the MOS devices using standard curve fitting techniques. Models then can be used for determining delays within the circuit.

Abstract: A method and apparatus introduces the creation and use of two record addressing functions. One function “computeRID” assigns identifiers to records, and the other function “lookupRID” performs the related task of locating a record given its identifier.

Abstract: A system to mount several electronic devices within a one EIA unit high rackspace is presented. The system includes a mounting chassis that is securely fastened to a standard 19″ EIA electronics rack. The chassis includes dividers that define at least two full length ports in which the electronic devices are slidably engaged. Furthermore, each port defined by the mounting tray includes hot-pluggable, blind-mate sockets to receive corresponding hot-pluggable, blind-mate connectors upon each electronics package. These packages are engaged and disengaged to and from the ports within the rack at will, thus allowing for more servers to be efficiently and accessibly stored within the confines of a 1-U rackspace with interchangeability than was previously possible.

Abstract: Computer method and apparatus allows instrumentation of program modules while maintaining exception-handling unwinding context. In the case of instrumenting procedure prologues, the invention preserves the calling context. A sanitized copy of the prologue and rewind instructions to reverse the effects of duplicate prologue instructions are employed.

Abstract: A computer system having thermal control logic that efficiently cools the computer system. In accordance with one embodiment of the invention, the thermal control logic couples to a CPU module and a fan. The CPU module includes a pair of temperature response elements. One temperature response element located near or on the CPU core logic or die on which the CPU is fabricated. The other temperature response element is located near or on an exterior surface of the CPU module. The thermal control logic monitors the temperature of recorded by each temperature response element and controls the speed of the fan and the frequency of the CPU core clock independently. Preferably, the thermal control logic adjusts the fan speed as a function of the temperature recorded by the temperature element adjacent an exterior surface of the CPU module. The thermal control logic also adjusts the frequency of the CPU clock signal as a function of the temperature recorded by the temperature response element adjacent the CPU core.

Abstract: In one aspect, the invention is a battery fuel gauge for a cache card comprising a charging circuit for charging at least one battery and a decrementor circuit for counting the amount of time system power is removed from the battery.

Abstract: Systems and methods for supporting and maintaining a distributed global map of transaction identifiers at the gateway processes using a hashing algorithm configured on each application process to access the global maps. A global map of transaction identifiers that associates global transaction identifiers with remote local transaction identifiers is maintained at each gateway process. When an application process performing work for a particular transaction desires to export the transaction to a remote node, a hashing function configured on the application process is applied to the global transaction identifier associated with the particular transaction. Application of the hashing function to the global transaction identifier identifies one of the gateway processes. The global transaction identifier is stored to the global map associated with that gateway process.

Abstract: Methods and arrangements are provided for allowing various devices to communicate data over standard twisted pair wire within a confined region, such as a home environment. The methods and arrangements employ radio frequency (RF) communication techniques to modulate and transmit data signals over existing twisted pair phone lines at RF frequencies. The RF transmitted data can be detected over limited distances by other similarly configured devices. The RF transmitted data is then received and demodulated to regenerate the original data. The methods and arrangements also allow the data transmission to be conducted in accordance with conventional CSMA/CD techniques/protocols. Thus, for example, Ethernet network configured devices can be seamlessly interconnected using the methods and arrangements of the present invention without requiring that additional and/or upgraded wiring be installed in the home environment.

Abstract: An apparatus for identifying requests to main memory as non-cacheable in a computer system with multiple processors includes a main memory, memory cache, processor and cache coherence directory all coupled to a host bridge unit (North bridge). The processor transmits requests for data to the main memory via the host bridge unit. The host bridge unit includes a cache coherence controller that implements a protocol to maintain the coherence of data stored in each of the processor caches in the computer system. A cache coherence directory is connected to the cache coherence controller. After receiving the request for data from main memory, the host bridge unit identifies requests for data to main memory as cacheable or non-cacheable. If the data is non-cacheable, then the host bridge unit does not request the cache coherence controller to perform a cache coherence directory lookup to maintain the coherence of the data.

Abstract: A computing environment (2) includes multiple CPUs (5a-c), multiple nonshared memory spaces and a means for implementing a select system call (10a-c).

Abstract: A multi-threaded processor comprising a pipeline including a number of stages processing instructions belonging to a plurality of threads. A buffer stores instructions from different ones of the threads. Count logic stores count information relating to each of the threads to indicate the number of instructions in each of the corresponding threads that have a particular attribute. A selection logic circuit has an output coupled to the buffer to determine which instruction is to be read from the buffer based on the count information stored by the count logic. The count information may, for example, provide information relating to a likelihood that one or more instructions belonging to each of the threads will be cancelled; relating to a count of unresolved branch instructions; or relating to a count of outstanding data cache misses. In operation, a thread may be selected for execution based on a selected attribute to enhance processing performance.

Abstract: A computer implemented method is applied to convert a formatted document or text to an ordered list of words. The formatted document is first partitioned into first and second data structures stored in a memory of a computer. The first data structure stores text fragments, and the second data structure stores code fragments of the formatted document. Adjacent text fragments are concatenated to form possible ordered word lists. Possible words are matched against a dictionary of representative words. A best ordered word list having the fewest number of words is selected from the possible ordered word lists.

Abstract: A method and apparatus to layout planar magnetic coils on a PCB consists of maximizing the layer to layer overlap, and consequently maximizing total inductance for the given layout area, by spiraling alternating layers inward and outward. A further benefit of the matching opposite spirals is the ability to make the layer to layer electrical contacts within the magnetic field area, thus reducing leakage inductance, and minimizing the wasted extra conductor line length needed to make the connections outside the magnetic field. The reduced conductor line length results in reduced conductor line resistance. The method is applicable to voltage transformers and isolation transformers as well as simple inductors and other magnetic devices. In the transformer case the odd numbered layers are typically connected together in series to provide a larger turn ratio, and the even numbered layers are typically single turns (i.e., no spiral) connected together in parallel to provide more current capability.

Abstract: A semi-mobile desktop personal computer incorporating the features of a desktop personal computer with the mobility of a mobile personal computer. The computer comprises an elongated enclosure having a microprocessor therein.

Abstract: In a computer system including one or more hosts coupled via a host bus to each other and a cached host memory, an Input/Output processor providing data to peripheral devices and an I/O bus disposed between the hosts and the Input/Output processor for transfer of information therebetween, an inbound queue structure receives message information from one of the hosts, and an outbound queue structure sends message information from the I/O processor to one of the hosts. Each of the queue structures comprises a pair designated as a free-list buffer and a post-list buffer. The free-list buffer of the inbound queue structure and the post-list buffer of the outbound queue structure are locally coupled to the hosts so that message information transfers between these two buffers and the hosts without incurring I/O bus read operations.