Abstract: The SQL compiler and SQL executor in a database management system are extended to execute statements for dequeuing rows from a database table and statements that both updating tuples and return those tuples to a calling application. During execution of a select statement that includes an embedded update or delete operation, a table access operator accesses a defined range of rows in a database table. The table access operator receives from a calling application a request for rows dequeued from the database table. The table access operator responds to the requests for rows by returning to the calling application qualifying rows, if any, from the database table and also by performing the embedded delete or update operation. The SQL executor returns control to the calling application only after all rows deleted or updated by the table access operator have been sent to the calling application.

Abstract: In a first aspect, the invention is a method for interfacing a generic program with the ASL code in an ACPI system. The method comprises storing information from a generic program in a shared memory; accessing the ASL code; and retrieving the stored information with the ASL code. In a second aspect, the invention is a method for testing ASL PnP code in an ACPI system. The method comprises identifying a configurable PnP device; disabling the identified configurable PnP device; testing the disabled, configurable PnP device for a configuration; and verifying that, for the tested configuration, the resulting current resources match the set resources. In variations of these aspects, the methods may be performed by instructions encoded on a computer-readable, program storage medium and used to program a computer.

Abstract: In a data processing system of the type having multiple processor units coupled to one another by a bus means for interprocessor communications there is provided a fiber optic interconnection system to interconnect the bus means of multiple processor sections to one another, thereby allowing groups of the processor units to be physically spaced from one another. The fiber optic interconnect system includes, for each multiprocessor unit section functions to receive messages communicated on the interprocessor bus of that section for receipt by a destination processor of the other section, format the message for fiber optic transmission, and transmit the message; and circuitry for receiving messages on the fiber optic link, scheduling the message for transmission to the destination processor, and maintaining that scheduling in the face of receipt of another message for the same processor unit.

Abstract: A system, method and computer program product for hardware assisted backup for a computer mass storage subsystem wherein files to be backed up from a source storage medium (e.g. disk) to a formatted storage medium (e.g. tape) are written in logical block number (“LBN”) order regardless of the file's on-disk layout. If the source file structure information is available it is used or the disk blocks containing the file structure are marked in a used (or “free”) block bit map which may then be modified to exclude files that are “open for write”, marked as “no backup” or not part of the selected file save operation. In operation, the blocks are written to tape using a Tape Copy Data (“TCD”) command. Blocks that were selected, but excluded as “open for write” may then be written to the tape utilizing more conventional methodologies.

Abstract: In a chip multiprocessor system, the coherence protocol is split into two cooperating protocols implemented by different hardware modules. One protocol is responsible for cache coherence management within the chip, and is implemented by a second-level cache controller. The other protocol is responsible for cache coherence management across chip multiprocessor nodes, and is implemented by separate cache coherence protocol engines. The cache controller and the protocol engine within each node communicate and synchronize memory transactions involving multiple nodes to maintain cache coherence within and across the nodes. The present invention addresses race conditions that arise during this communication and synchronization.

Abstract: A computer system adapted for hot-pluggable components such as memory modules that may be replaced, upgraded and/or added without disturbing normal operation of the computer system. A failing memory module may be replaced by copying its contents to a new memory module in a background operation while the computer system runs its operating system and applications programs. When all contents are copied to the new memory module, the failing memory module may be removed without having to shut down the computer system. Computer system memory may be upgraded or added to by inserting the new memory module(s) into vacant disconnected memory connectors, whereupon the computer system automatically recognizes the new memory module(s), synchronously connects the new memory module(s) to the computer system memory bus, initializes the new memory module(s), and then notifies the operating system that the new memory module(s) is available, all without disturbing normal operation of the computer system.

Abstract: A sense amplifier is provided for sensing an input voltage level of a data signal. Such a sense amplifier pre-charges, and subsequently discharges, a pair of nodes through a respective pair of discharge paths. Each of those discharge paths is capable of performing the discharge operation at a rate that is related to either a system voltage supply or an input logic level of the data signal. Because the discharge path that is associated with the data signal includes a greater amount of conductance, it can perform the discharge operation at a faster rate, even where the input logic level does not exceed the voltage of the system voltage supply. A determination is made as to which of the discharge is the faster and, responsively, a rail-to-rail output signal having the same polarity as the data signal, is generated. The input data signal is conveyed to the sense amplifier by a single wire. Also, the sense amplifier does not require a specialized reference voltage for proper operation.

Abstract: A high speed connection apparatus, method, and system is provided for peripheral components on digital computer systems. The peripheral component interconnect (PCI) specification is used as a baseline for an extended set of commands and attributes. The extended command and the attribute are issued on the bus during the clock cycle immediately after the clock cycle when the initial command was issued. The extended commands and attributes utilize the standard pin connections of conventional PCI devices and buses making the present invention backward-compatible with existing (conventional) PCI devices and legacy computer systems. Alternate embodiments of the present invention utilize a side-band address port (SBA port) to enable multiple targets to receive the same set of data. The conventional PCI command encoding is modified and the extended command is used to qualify the type of transaction and the attributes being used by the initiator of the transaction.

Abstract: A computer system with various component modules with each of the modules interconnected with a single midplane board, thereby eliminating the need for ribbon cables to interconnect between the modules. One of the modules includes an embedded controller and associated data bus. An in-line connector is coupled in the data bus which receives either a jumper connector or interconnect connector. The interconnect connector intercepts the data bus from the embedded controller and transfers connection to a user added controller. The interconnect connector can operate in two modes, a single mode and a differential mode. The interconnect connector includes logic circuitry that determines the type of controller connected and places the interconnect connector in the appropriate mode. If the logic circuitry detects that a single-ended controller is connected to the interconnect connector, a quick switch, which is connected to one wire of the data bus, is closed, thereby grounding the one wire.

Abstract: Apparatus and method are disclosed for down scaling performance of a multibus multiprocessor computer system. One or more busses associated with one or more failed processors or devices are disabled to allow operation from remaining busses. If errors or power failure are detected in a processor or bus device the computer system may reboot and, using the apparatus and method of the present invention, the bus associated with the defective processors or devices may be disabled upon reboot. The one or more affected busses may be disabled and the computer system may be brought back up in a single-bus operational mode or a multiple bus operational mode where an alternate bus is designated as the boot bus.

Abstract: In a multiple processing system or cluster, a pair of processes, assuming the role of a primary process and a backup process to the primary process, are replaced on-line by stopping the backup process; creating the replacement backup process; checking to ensure compatibility between the primary and replacement backup processes so that communication between them is possible and information sent by the primary process to the replacement will be correctly received and handled; providing the replacement backup process with that state of the primary process needed in order to take over the function and operation of the primary process; switching roles so that the replacement backup process now takes over the function and operation of the primary, and the primary becomes the backup; and repeating the steps of creating, checking, providing and switching, to conclude with a newly-installed replacement primary process and a replacement backup process, completing the on-line replacement of the process pair.

Abstract: A technique for handling a conditional move instruction in an out-of-order data processor. The technique involves detecting a conditional move instruction within an instruction stream, and generating multiple instructions according to the detected conditional move instruction. The technique further involves replacing the conditional move instruction within the instruction stream with the generated multiple instructions. The generated multiple instructions are generated such that each of the generated multiple instructions executes using no more than two input ports of an execution unit. The generated multiple instructions include a first generated instruction that produces a condition result indicating whether a condition exists, and a second generated instruction that inputs the condition result as a portion of an operand which identifies a register of the out-of-order data processor.

Abstract: Each node of a multiprocessor computer system includes a main memory, a cache memory system and logic. The main memory stores memory lines of data. A directory entry for each memory line indicates whether a copy of the corresponding memory line is stored in the cache memory system in another node. The cache memory system stores copies of memory lines and cache state information indicating whether the cached copy of each memory line is an exclusive copy. The logic of each respective node is configured to respond to a transaction request for a particular memory line and its corresponding directory entry, where the respective node is the home node of the particular memory.

Abstract: A method for undeleting files in a computer system includes flagging at least one deleted file with an identifier. The flagged deleted file is hidden in the computer system. A list of deleted files that have been flagged with the identifier is generated. The list of deleted files is comprised of a directory path hierarchy for each deleted file. A file is selected from the list of deleted files and undeleted.

Abstract: A language translator is provided which determines memory structure at compile time for a plurality of object classes including at least one virtual base class and at least one class derived therefrom. At compile time, space for pointers (b-pointers) is set aside in each class object that will have a base table (b-table) associated therewith. The b-pointers point, at run time, to an associated b-table containing memory offsets between the base classes of the derived class. At run time, constructors construct the class objects, starting from the most derived class object and proceeding through to the base class object. However, instead of generating the virtual tables and associated pointers, as well as the adjusting functions, at compile time, the language translator generates the code for these operation to be executed at run time. Then at run time, a virtual function table is generated for the base class.

Abstract: A cabinet system includes first and second cabinets each including first and second side walls, upper and lower rectilinear frames extending between the side walls at vertically spaced-apart locations therealong and weldments connecting the upper and lower frames to the side walls to form a rigid housing. A pair of spaced-apart locating holes are formed in the side wall of the first cabinet adjacent to the lower frame thereof and an additional locating hole is present in the first wall of the first cabinet adjacent to the upper frame thereof. Further, a pair of spaced-part locating pins are provided in the second side wall of the second cabinet adjacent to the lower frame thereof along with an additional locating pin in the side wall of the second cabinet adjacent to the upper frame thereof.

Abstract: A computer system provides a self-modifying synchronization memory address space and protocol for communication between multiple busmasters. In one computer system embodiment, the self-modifying synchronization memory address space is provided in a memory controller embedded in a peripheral device of the computer system such as a bridge that provides central, high speed access by a busmaster to the memory controller without accessing a host bus. The synchronization memory address space includes a set of semaphore memory cells mapped to shared critical resources in the computer system. The semaphore memory cell allows for exclusive access by a busmaster to a shared critical resource by switching itself from an idle state to a busy state responsive to a first read operation by a busmaster. In the busy state of the semaphore memory cell, a busy state is communicated to other busmasters which attempt to read the semaphore memory cell.

Abstract: A technique controls memory access requests. The technique involves acquiring a first series of requests including a prefetch request for performing a prefetch operation that prefetches a first set of instructions from a memory, and adding a first entry in a request queue in response to the prefetch request. The first entry identifies the prefetch operation. The technique further involves attempting to retrieve a second set of instructions from a cache to create a cache miss, and generating, in response to the cache miss, a second series of requests including a fetch request for performing a fetch operation that fetches the second set of instructions from the memory to satisfy the cache miss. The technique further involves acquiring the second series of requests that includes the fetch request, and adding a second entry in the request queue in response to the fetch request. The second entry identifies the fetch operation.

Abstract: A system and method to reduce power. consumption in a portable computer system while allowing the CDROM drive to continue playing audio CDs. When the system enters a suspend mode, the status of the CDROM drive is checked, and if it is playing an audio CD, it remains powered, otherwise power to the CDROM drive, is also suspended. The system recognizes when the audio CD is finished playing and then places the CDROM drive into the suspend mode.

Abstract: A computer system includes a graphics controller with a first refresh rate and a first horizontal synchronization signal; a secondary source of video data having a second refresh rate and a second horizontal synchronization signal; and a genlock unit for reconciling the first refresh rate of the graphics controller with the second refresh rate of the secondary source. The genlock unit outputs a clock signal with a frequency modulated to reconcile the first refresh rate and the second refresh rate by monitoring the phase differences of the first horizontal synchronization signal and the second horizontal synchronization signal in response to a first control signal and outputs a clock signal at a frequency corresponding to a selected clock frequency in response to a second control signal.