Abstract: A method and apparatus for testing integrated circuit devices includes a cooling chuck which is extensible within a bore in a cooling chuck body to a position in thermal contact with the integrated circuit device. The temperature of the cooling chuck is regulated by a fluid cooling system, which can be set to operate at a selected capacity to maintain the integrated circuit device at a desired temperature during testing.

Abstract: A cam actuated electrical connector includes a pin housing, a terminal housing and an elongate cam extendable transversely through the terminal housing for moving shuttle assemblies toward and into electrical engagement with the pin housing.

Abstract: A READ-WHILE-WRITE current-mode logic RAM cell suitable for use in a RAM device having the ability to simultaneously write and read data.The RAM cell contains a bit-cell consisting of flip-flop configured transistors differentially connected to a constant current source, a multiple-emitter transistor network tied to each bit-cell load resistor which prevents the bit-cell from saturating, separate READ and WRITE data lines, and READ and WRITE buffer transistors having READ and WRITE control lines.

Abstract: Improved performance and reliability is obtained in test sockets for integrated circuits (ICs). Sufficient over-travel is provided to prevent pinching when the IC and its carrier are inserted in the test socket and the lid is latched closed. A power operated piston applies controllable and uniform pressure to force the IC leads onto contact pins in the test socket base. This controllable and uniform pressure prevents gouged IC leads, bent test socket pins, and other damage that prevents proper electrical and mechanical contact between IC leads and contact pins resulting in erroneous indications of faulty IC operation.

Abstract: A nibble-mode DRAM solid state storage device is organized into a plurality of sections each including a plurality of groups, each including a plurality of ranks of DRAM memory chips. A pipeline data path is provided into and out of each group and nibble-mode access is facilitated by simultaneous pipelining of data into and out of the memory while memory reference operations are accomplished.

Abstract: A generic chip carrier is described which includes, as integral parts, a voltage bus and a plurality of terminating resistors connected between the voltage bus and signal traces on the carrier. The voltage bus wraps around the chip carrier, thus providing a large area of metal. Through the selective use of the terminating resistors, the generic carrier can be customized for a particular type of integrated circuit, i.e., source or destination termination of signals. A signal trace may be customized by "opening" the terminating resistor with a current spike applied by a standard electrical probe. Spare bonding pads and terminating resistors are placed at intervals about the periphery of the carrier as insurance against defective or mistakenly removed terminating resistors.

Abstract: An improved multiple circuit module for use in an electronic device includes a number of cold plates sandwiched between pairs of circuit boards for taking away excess heat from the circuit boards. Each plate is provided with open spaces which permit communication between the circuit boards, and with circuit boards on other cold plates. Electrical communication between the circuit boards is effected by an array of metallic pins. The pins are received in a perforate pin header which extends along the depth of the cold plate, and pins communicating with other circuit boards extend into a connector block which is placed between a pair of pin headers. Shielding is provided in both the connector blocks and pin headers to prevent electronic cross-talk between pins disposed therein. In one embodiment, a novel type of pin which reduces installation and disconnection friction is utilized.

Abstract: The present invention provides a parallel board connector having zero insertion force between a PC board and a backplane which presents effectively zero impedance change through the connector interface. The PC board and the backplane to which it is to be connected have through-plated holes. The boards are positioned to overlap such that the through-plated holes are axially aligned. A shuttle block is provided with a number of parallel dual flex pins attached to one surface. To effect connection, the flex pins of the shuttle block are inserted through the holes of one board and into the holes of a second board to provide an electrical connection having very low or no impedance interface.

Abstract: A multiprocessing system and method for multiprocessing is disclosed. A pair of processors are provided, and each are connected to a central memory through a plurality of memory reference ports. The processors are further each connected to a plurality of shared registers which may be directly addressed by either processor at rates commensurate with intra-processor operation. The shared registers include registers for holding scalar and address information and registers for holding information to be used in coordinating the transfer of information through the shared registers. A multiport memory is provided and includes a conflict resolution circuit which senses and prioritizes conflicting references to the central memory. Each CPU is interfaced with the central memory through three ports, with each of the ports handling different ones of several different types of memory references which may be made.

Abstract: A cooling plate for heat dissipation is particularly adapted for use within printed circuit board stacks. The cooling plate includes a fluid inlet manifold, fluid pass containing a plurality of heat dissipation fins, and a fluid outlet manifold. Externally, the cooling plate has a pattern of heat conductive pads that is substantially identical to the pattern of devices on a printed circuit board attached to the cooling plate. The cooling plate includes apertures and mounting elements for z-axis connector assemblies so that printed circuit boards attached to either side of the cooling plate may electrically interconnect.

Abstract: An apparatus and method for creating a stack assembly of print circuit boards and for providing electrical interconnection between the individual through-plated hole pads of the circuit boards is described. The preferred embodiment of the present invention is a device comprised of two parts: a slotted disk and a wire. The slotted disk is attached to the surface of the printed circuit board so as to cover a hole pad and form an electrical connection therewith. The covered holes of the printed circuit board are axially aligned between circuit boards and an electrically conducting wire is inserted through the slotted disks on the circuit boards to form an electrical connection therewith.

Abstract: A connector frame for use in the connection of electrical circuit assemblies having pins integrally connected therewith. The connector frame is a body of electrically non-conductive, thermally conductive material having one or more apertures bored through the body, said apertures being through-plated with an electrically-conductive material having a lower melting point than any of the surrounding materials. Said body also includes at least one separate aperture in which is disposed an electrically-conductive, heat-generating wire, said wire having the capacity to generate sufficient heat to melt the electrically-conductive material disposed in the apertures to form a strong electrical and mechanical bond between the pins of the electrical circuit assemblies.

Abstract: A peripheral interface system is disclosed. An input-output processor is provided to receive input-output commands from a central processing unit. Up to four multiplexing units may be connected to the input-output processor, with each multiplexing unit providing an interface for up to four controller units, which may be used to control a peripheral device. The multiplexing unit includes a pair of data buffers, each with its own addressing circuit, and each functionally divided into four storage areas, each storage area providing four registers to store four parcels of data. Data is transferred between the input-output processor and the controller units by filing the storage area in a buffer from the local memory of the input-output processor in a serial fashion over a DMA channel provided between the multiplexer and the local memory.

Abstract: A personnel antistatic test device includes a conductive shoe plate adapted to be stood upon by the person to be checked, a jack for receiving the plug of a wrist strap worn by the person to be checked, and circuitry for measuring effectiveness of static discharge paths through the wrist strap and through the person's footwear. Electrical circuitry is provided for measuring resistance from a touch plate, through the person's body, through the wrist strap and its lead wire. In the footwear checking mode, resistance is measured from the touch pad through the person's body, through the stockings and shoes to the shoe plate. Appropriate resistance range values are provided for the wrist strap and shoe check mode, and indicator lights are activated showing a satisfactory static discharge path, a hazard condition due to low resistance, or an unacceptable static discharge path due to high resistance.

Abstract: A safety monitoring system for an immersion cooling system of a large, high-density electronic assembly such as a supercomputer protects against the possibility of toxic gas formation due to overheating and breakdown of the cooling liquid caused by a system failure. Voltage taps are provided on all of the power supply bars in the computer, and are brought out to the monitoring system, which scans them and compares them against predetermined voltage tolerance limits. A catastrophic electronic failure or short circuit within the computer could produce arcing that could cause local high temperatures and coolant breakdown. The reduction in voltage caused by such failure would immediately be detected by the monitor, which would operate to shut down power to the computer, and activate a safety ventilation system prior to any substantial production of toxic gas.

Abstract: A data modulation interface is provided for serial data transmission. A biphase signal is encoded with the binary bits of a parallel data word. The bits of the parallel data word are examined to determine whether there are more one bits or zero bits in the word. A polarity bit is provided in addition to the other bits to indicate which bit-state occurred most often. The biphase signal is modulated to create different time intervals between phase reversals with one time interval corresponding to a bit-state of one and another time interval corresponding to a bit-state of zero. The shortest time interval is assigned to correspond to the bit-state occurring most often in the word so that the total time required to transmit each word is minimized. A time interval can be assigned to a sync signal transmitted after each parallel data word. A time interval can also be assigned to correspond to plural bit combinations so they can be represented by a single phase interval and transmitted quickly.

Abstract: An electrical interface system provides a set of signals to be used in transferring information between first and second terminals. To transfer information from the first terminal to the second terminal, a WRITE CLOCK, FUNCTION/DATA READY, four CODE, one CODE PARITY, 16 DATA and DATA PARITY signals are provided. To transfer information from a second terminal to the first terminal, a READ CLOCK, STATUS/DATA READY, ERROR, DONE, INDEX/SECTOR MARK, STATUS PARITY, 16 DATA and one DATA PARITY signals are provided. The four CODE signals may be formed to signal any one of a plurality of requested functions to the second terminal, while the second terminal may indicate its general status to the first terminal with the ERROR, DONE, READY and MARK signals, each terminal capable of further defining functions or status by formation of words with the data signals.

Abstract: An interprocessor communication system for a multiprocessor data processing system includes a common control circuit which includes a plurality of clusters where each cluster includes a plurality of semaphore registers and a plurality of information registers. Each type of register may be directly addressed by any processor. Each processor has a cluster code indicative of which, if any, of the clusters the processor may access. Each processor has a local control circuit in relatively close physical proximity and each local control circuit can communicate with the other local control circuits to determine whether one of its counterparts is requesting an operation. The local control circuit monitors and controls the issuance of the processor's instructions to the common control circuit. The local control circuit includes a plurality of local semaphore registers maintained with a copy of data in the common semaphore register cluster associated with that processor.

Abstract: A memory interface and conflict resolution network for a multiprocessor system. The memory is multisectional and each section of memory has a plurality of individually addressable memory banks organized in an interleaved fashion and a section level conflict resolution network. Each processor in the system includes several ports and a gating network such that each port may access any section of memory, but access is restricted to no more than one reference per processor per clock period to each section of memory. References generated from different ports of the same processor are automatically synchronized. Each processor has a conflict resolution circuit to resolve conflicts between different ports seeking access to the same section of memory.

Abstract: An electrical edge connector (14) of the zero insertion force type includes a pair of opposing blocks (30, 32) defining a longitudinal guideway (34) therebetween. Opposite corresonding pairs of female contacts (52, 54) are disposed in transverse holes in the blocks (30, 32), and male contacts (60) are slidably supported in the female contacts in one block for selective actuation into or out of sliding engagement with the female contacts in the other block responsive to insertion of a slider (36).