Abstract: A pair of processors are each connected to a central memory through a plurality of memory reference ports. The processors are further each connected to a plurality of shared registers which may be directly addressed by either processor at rates commensurate with intra-processor operation. The shared registers include registers for holding scalar and address information and registers for holding information to be used in coordinating the transfer of information through the shared registers. A multiport memory is provided and includes a conflict resolution circuit which senses and prioritizes conflicting references to the central memory. Each CPU is interfaced with the central memory through three ports, with each of the ports handling different ones of several different types of memory references which may be made. At least one I/O port is provided to be shared by the processors in transferring information between the central memory and peripheral storage devices.

Abstract: A logic system preferably for gallium arsenide integrated circuits uses dynamic pulsed logic gates which switch on each clock pulse, with the logical state of an output or data line being indicated by the phase of the pulsed output, which may be shifted or modulated with respect to a reference. An individual logic gate has a first signal generator having a capacitor which is either charged up or discharged during a set-up phase of a clock cycle, depending upon applied input logic signals. During a second, transmit phase of the clock signal, the signal developed on the capacitor is output from the gate. A second signal generator is an inverting slave of the first, and outputs the inverse logic state during the succeeding set-up phase of the first generator. With each gate switching on every clock period, all switching noise appearing in the ground or power supplies is at or above the clock frequency and can simply be filtered out with small chip capacitors, providing improvement in noise immunity.

Abstract: A multiprocessing system and method for multiprocessing is disclosed. A pair of processors are provided, and each are connected to a central memory through a plurality of memory reference ports. The processors are further each connected to the plurality of shared registers which may be directly addressed by either processor at rates commensurate with intraprocessor operation. The shared registers include registers for holding scalar and address information and registers for holding information to be used in coordinating the transfer of information through the shared registers. A multiport memory is provided and includes a conflict resolution circuit which senses and prioritizes conflicting references to the central memory. Each CPU is interfaced with the central memory through three ports, with each of the ports handling different ones of several different types of memory references which may be made.

Abstract: A solid state storage device is disclosed. The storage sections of the device are divided into two groups, with each group including at least one, and as many as four storage sections. A port is provided for delivering words to and receiving words from the sections. A data path between the port and the device is two words wide, with one word received from or delivered to each group. Each section includes a word storage register, with the registers of different sections in the same group being connected in a series fashion to provide a one word data path between the storage sections. Words stored or retrieved from a section are passed through its respective register. In a write operation, words to be stored are transmitted serially from register to register and captured by all sections simultaneously on the same clock cycle. Addressing means within each section then routes the word to the appropriate memory circuit within the section.

Abstract: A circuit module (10) having enhanced heat transfer and distribution characteristics which is particularly adapted for use in high speed electronic digital computers. The circuit module (10) includes a circuit board assembly (12) with a plurality of electronic devices (26) such as integrated circuits, mounted on a circuit board (28). The circuit board (28) includes conductive pads (42 and 44) and plated-through holes (46) forming a thermally conductive flow path from each electronic device (26) to the opposite side of the circuit board for more efficient heat transfer away from the module (10). The heat pads (42 and 44) and plated-through holes (46) are preferably connected with the ground plane layer (36) of the circuit board (28) for better heat distribution as well.

Abstract: An immersion cooling system for high density electronic assemblies such as computers includes a container holding an inert cooling liquid, and stacks of circuit modules arranged in a generally radial pattern within the container. Coolant supply columns and coolant removal columns alternate between adjacent stacks around the pattern. The coolant supply columns include distribution manifolds which distribute incoming coolant at all levels to provide a flow of coolant to all circuit modules. The flow passes between adjacent boards of the modules and preferably along flow channels formed by the circuit chips aligned in rows. After passing across the circuit modules the heated coolant rises in coolant removal columns and flows over standpipes for removal from the container, and a pump and heat exchanger recools and recirculates the coolant. Pump up and pump down systems are also provided for withdrawing the coolant to a reservoir for servicing the circuitry.

Abstract: A circuit module (10) having enhanced heat transfer and distribution characteristics which is particularly adapted for use in high speed electronic digital computers. The circuit module (10) includes a circuit board assembly (12) with a plurality of electronic devices (26) such as integrated circuits, mounted on a circuit board (28). The circuit board (28) includes conductive pads (42 and 44) and plated-through holes (46) forming a thermally conductive flow path from each electronic device (26) to the opposite side of the circuit board for more efficient heat transfer away from the module (10). The heat pads (42 and 44) and plated-through holes (46) are preferably connected with the ground plane layer (36) of the circuit board (28) for better heat distribution as well.

Abstract: The specification discloses an interconnected multiple circuit module (10) including a connector assembly (14) for interconnecting two circuit modules (12) each having at least one circuit board assembly (16). The connector assembly (14) includes pins (26) extending through the circuit board assemblies (16) and a free connector block (28) for receiving the pins in opposite ends. The pins (26), connector block (28) and contacts (40) within the block are preferably adapted to provide differential mechanical resistances on opposite ends of the block between the pins to facilitate controlled predictable electrical connection of the circuit modules (12).

Abstract: An improved cooling system for electronic assemblies provides cold bars (10) and cold plates (60) for supporting and conducting heat away from a plurality of electronic assemblies (12, 52) attached thereto. A plurality of refrigerant holes (A-F, 70-77) are drilled through the cold bar or plate. End caps (27, 28, 61, 62) have well-like areas forming refrigerant return passages that cooperate with the cold bar or plate to interconnect individual refrigerant holes or groups of holes to form multiple pass refrigerant paths through the cold bar or plate to external connections for connecting to a refrigeration system. The holes are preferably threaded to improve heat transfer characteristics. The pattern, sizing, and grouping of holes can be varied to adjust the design of a particular cold bar or plate to the heat load of a given application.

Abstract: Vector processing in a computer is achieved by means of a plurality of vector registers, a plurality of independent fully segmented functional units, and means for controlling the operation of the vector registers. Operations are performed on data from vector register to functional unit and back to vector register with minimal delay, rather than memory to functional unit and return to memory with its attendant much greater start-up delays. Data may be bulk transferred between memory and some vector registers while other vector registers are involved in vector processing with one or more functional units. In vector processing elements of one or more vector registers are successively transmitted as operands to a functional unit at a rate of one per clock period, and results are transmitted from a functional unit to a receiving vector register at the same rate.

Abstract: The chassis for an electronic assembly includes a plurality of cooling bars which are mounted parallel to each other and spaced apart to receive electronic assembly modules. The cooling bars have internal passages for the flow of coolant, and the bars have a plurality of slots formed in the sides thereof facing adjacent cooling bars. The electronic assembly module in the preferred embodiment comprise a pair of circuit board assemblies with a heat conducting plate sandwiched therebetween, and extending slightly beyond the margins of the circuit boards to form heat conducting flanges along opposing sides of the module. The circuit modules are positioned between adjacent cooling bars with the heat conducting flanges fitting in the slots of the cooling bars. Clamping means force the heat conducting flanges into intimate thermal contact with the slots of the cooling bars. In a preferred embodiment, the clamping means comprises a plurality of wedge blocks which are cammed into the flanges.