Abstract: A fault tolerant network for a plurality of computers includes a system for controlling access to shared peripherals. Access to the shared peripherals is coordinated among the computers by means of communication through a semaphore box. Each computer connects to the semaphore box via a channel. The semaphore box is comprised of two major sections: a semaphore section and an I/O section. The semaphore section contains two sets of semaphores: a first set comprising reservation semaphores for the shared peripherals; and a second set comprising heartbeat semaphores for the sharing computers. The first set is used to reserve a particular peripheral for a particular computer and indicate the source of the reservation; the second set provides a "heartbeat" to prevent reservation semaphores from being set indefinitely in the event communication with a particular computer is lost.

Abstract: A method of memory access for sharing a memory between multiple processors. The memory comprises a plurality of sections and each section is connected to each processor by a memory path. Each section includes a plurality of subsections and each subsection includes a plurality of banks which includes a plurality of individually addressable memory locations. Memory references attempting to access the individually addressable memory locations are generated by the processors. Subsection conflicts between the memory references generated by a plurality of ports of each processor are resolved so that only one of the memory references from each processor is allowed to access one of the plurality of subsections at a time. Section conflicts between the memory references generated by the plurality of ports of each processor are resolved so that only one of the plurality of ports of each processor connects by the memory path for each processor to one of the plurality of the sections at a time.

Abstract: Silicon is used to create multi-chip carriers for integrated circuits. The process of fabricating the carriers uses standard integrated circuit fabrication equipment. Cavities are etched into a silicon wafer, metallization or polysilicon is deposited to electrically interconnect the cavities, and integrated circuit die are placed in the cavities. Traces connecting the integrated circuits are buried in channels formed in the silicon, which can be doped and biased to provide enhanced isolation between traces as well as control over the electrical characteristics of the traces. The traces can be formed in multiple layers of material placed on the wafer to provide additional communication capacity in the carriers.

Abstract: An apparatus and method of making a beam of directed energy used to bond leads to bonding areas is disclosed. The masking tool preferably includes a groove adapted to allow the beam to strike the lead while masking the surrounding substrate to prevent damage to it. The tool preferably reflects the energy striking it away from the substrate. The method can include the use of an external heat source to provide heat to the bonding process or, in the alternative, provide heat sinking to protect the electrical components from heat damage. Alternate embodiments of the tool can include a plurality of grooves or slots to allow scanning of the beam in the bonding process.

Abstract: The present invention provides an improved method for manufacturing circuit boards with high power, high density interconnects. Printed circuit board technology, integrated circuit technology, and heavy-build electroless plating are combined to produce multilayer circuit boards comprised of substrates with different interconnect densities. In the higher density substrates, thick metallized layers are built-up by combining additive and subtractive techniques. These thicker foils minimize DC voltage drop so that conductors can run for longer distances. The conductors are substantially more square than their thin film equivalents, thus providing better performance for high frequency signals. Power distribution capabilities are enhanced by the present invention, so that circuit boards fully populated with dense, high-speed, high-power integrated circuits can easily be supplied with their necessary power requirements.

Abstract: A method for simultaneously manufacturing metallized carriers from wafer-shaped substrates is described, wherein such wafer-shaped substrates permit the use of standard IC fabrication apparatus and methods. As a result, very thin and finely dimensioned traces can be deposited. Thin-film manufacturing techniques are used to create the high-density traces on the surface of the chip carriers, thereby permitting direct connections from the IC to the periphery of the carrier without the need for vias. A lid hermetically seals and protects the package. The traces are comprised of a plurality of metals to facilitate bonding, each of the metals homogeneous for a portion of the trace. One metal portion of the trace is of a type compatible with an IC chip placed in the carrier. Another metal portion of the trace is of a type compatible with a trace on a printed circuit board. A metal barrier is interposed between the metals to prevent metal diffusion from one metal to an adjoining portion of another metal.

Abstract: Logic unit cells are disclosed, consisting of an array of high speed logic gates, the outputs of which are wired together and coupled to a low power driver. High speed and switching rates are achieved by using very fast logic gates which have no gain and make use of a wired logic function in order to effect two levels of logic without adding the propagation delay through another logic gate. These arrays of logic gates are coupled to drivers which restore logic levels and provide the necessary power for driving interconnect capacitances while consuming and dissipating a minimum of power in the process. Another logic circuit discloses an array of logic gates as inputs to another logic gate, the individual gates consisting of gallium arsenide components and having drivers built into the output stage of each gate.

Abstract: An ultrasonic transducer, bonding tool and method of bonding gold or gold plated leads to gold or gold plated bonding pads located on unheated substrates is disclosed. More particularly, the transducer of the present invention incorporates a modified transducer/tool interface which provides for increased durability as well as increased excursion control of any bonding tool placed therein. The bonding tool of the present invention includes a modified end having a raised pattern used to form an impression in the lead to be bonded to enhance gripping of the lead during bonding. The preferred methods include using the modified transducer and bonding tool to perform gold-to-gold bonding on unheated substrates while providing increased vertical clearance for bonding between structures.

Abstract: A completely shielded metallic connector block for use in multiple circuit modules of an electronic device. Electrical communication between the circuit boards is effected by an array of metallic pins which run through the blocks. The metal of the blocks can be held at ground or at a constant potential to increase the shielding between pins as well as maintaining voltage and ground planes at constant levels throughout the modules. The blocks are insulated from the pins and circuit boards by a non-conductive coating. In the preferred embodiment, the metal of the blocks is aluminum and the coating is a hardcoat anodizing.

Abstract: An ECL circuit is capable of simultaneously responding to single-ended and differential inputs. The ECL circuit comprises a single-ended input, a differential input, logic responsive to the single-ended and differential inputs for determining a digital output state, and an output for communicating the output state to external devices. Each input, i.e., the single-ended input and the two complementary portions of the differential input, provide a base voltage for a control transistor. In order to allow the single-ended input to override the differential input, the differential input has half the voltage swing of the single-ended input and the high level of the differential input is halfway between the high and low levels of the single-ended input. In this way, an active single-ended input will exert more control over the current paths than the differential input. When the single-ended input is inactive, the differential input will exert control over the current paths.

Abstract: A method and apparatus for real-time testing of a Tape Automated Bonded integrated circuit is described. The apparatus is inserted between a test board and a TAB tape integrated circuit. The beams of the assembly are arranged in a pattern similar to the pattern of the electrical contact pads on the test board and the TAB tape. When axial pressure is applied to the test board, the apparatus and the TAB tape, the beams compress and deform, thereby providing a scrubbing contact between the ends of the beams and the contact pads of the TAB tape and the test board. The beams are short in length thereby providing an electrical connection of virtually no impedance interface between the TAB tape and the test board, thereby allowing the intergrated circuit to be tested at AC speed.

Abstract: A method and apparatus provides bit manipulation of data in vector registers of a vector register computer system. Matrix multiplication is accomplished at a bit level of data stored as two matrices in a vector computer system to produce a matrix result. The matrices may be at least as large as 64 bits by 64 bits and multiplied by another 64 by 64 matrix by means of a vector matrix multiplication functional unit operating on the matrices within a vector processor. The resulting data is also stored at a 64 bit by 64 bit matrix residing in a resultant vector register.

Abstract: The invention comprises a plurality of stacked planar processing circuit boards surrounded on at least one side by a plurality of memory boards located substantially perpendicular to the planar processing boards, the processing and memory boards connected by orthogonal interconnect modules. The orthogonal interconnect modules allow closely-spaced orthogonal connection of the processing boards to the memory boards. The memory boards are of a densely packed design having a plurality of removeable memory chip stacks located on the memory boards.

Abstract: An air manifold mounted adjacent to a circuit board for directing air jets onto electronic devices mounted on the circuit board. The air manifold has an air inlet and a plurality of outlet nozzles positioned along the channel for directing air onto the electronic devices. A plurality of members are positioned next to the nozzles with the members increasing in length as the distance between the inlet and the outlets increase.

Abstract: Apparatus and method for determining the electrical length of a signal flow path, such as a twisted-pair conductor, to create conductors of the same electrical length are disclosed. The term electrical length refers to a certain physical distance for a length of conductor for which an electrical signal travels, or propagates along the conductor, in a specified amount of time. The apparatus preferably includes a Time Domain Reflectometer 25 (including pulse generator means 30 and electrical response display means 20) which is cooperatively connected to a first end of a conductor pair 51 under test. The conductor pair 51 is inserted through a ground plane 60 or other impedance changing device. Means to mark or cut 62 the conductor 51 are located within the ground plane 60 or as close as possible to the point at which the impedance is changed. Processing means 40 are utilized to adjust the conductor 51 length relative to the ground plane 60.

Abstract: Z-axis connectors for interconnecting stacked printed circuit boards are formed from resilient material and have contact sections larger than cooperating through-plated holes formed in the boards. The connectors are drawn through the through-plated holes in the stacked circuit board, causing the contact section of the connector to frictionally engage the through-plated holes on at least two boards.

Abstract: A functional unit composed of parallel data processing paths implemented in relatively low speed digital logic. A data processing path is designed in a digital logic family of high integration but relatively low speed. The path is designed to be clocked by a data processing clock where the frequency of the data processing clock is substantially the system clock divided by the number of parallel implementations of the data processing path.

Abstract: An optical backplane interconnects logic assemblies in a computer system using optical fibers. The logic assembly is connected to a laser or LED for converting electrical signals from the logic assembly into the equivalent optical signals. The optical signals are transmitted along the optical fibers to another logic assembly. The optical backplane comprises a mainframe rail for mounting to one end of the logic assembly, a connector attached to the mainframe rail, and an optical coupler mated with the connector. The optical coupler and connector having matching vee grooves for supporting and aligning the optical fibers.

Abstract: Improved error detection and correction is obtained in computers of the type possessing multi-bit memory devices. The error detection involves dispersing the bits from each multi-bit memory device in such a way that a SEC-DED codeword can detect when the multi-bit memory device fails.