Abstract: Four clusters of 16 CPU's each are each associated with a solid state memory and a main memory. Each CPU is uniquely associated with a channel arbitrator which interconnects the associated CPU to serial ports. Each channel arbitrator is associated with a set of 16 serial channels. Each serial channel is in turn interconnected to a channel adapter which includes software and firmware adapted for interacting with a specific peripheral device. Each channel adapter also has software and firmware which is device-independent for data transfer with the channel arbitrator. The channel arbitrator includes a memory port for accessing main memory through the CPU, a port for accepting service requests and providing interrupts to the CPU's, direct memory access control logic, arbitration control logic, serial ports associated with the channel adapters, and a parallel port is associated with solid state memory.

Abstract: The present invention provides a method and apparatus for handling memory hazards in processors having multiple memory ports wherein the operation of marking of the memory requests that may be related to a memory hazard is separated from the operation of waiting for the memory hazard to clear. The separation of the operation of marking of memory hazards from the operation of waiting for memory hazards to clear allows a compiler to schedule other instructions, as well as other memory operations not directed to the memory location involved in the memory hazard sequence, during the time between the operations of marking and waiting for the memory hazard to clear. The waiting period ends once it is clear that the marked memory requests will execute in the order in which they were issued.

Abstract: A method of implementing a privileged instruction that enables the development of new operating systems in user mode. The instruction decode logic includes a maskable interrupt generator that interrupts the processor during the processing of privileged instructions in user mode. An exception handler processes the privileged instruction interrupt and performs a function similar to the execution of the privileged instruction in privileged instruction mode. The combination of the privileged instruction interrupt and the post-interrupt exception handling enables the operating system developer to test new operating systems by laying them over the current operating system.

Abstract: A method for making an integrated circuit chip carrier having reduced and regulable interlead capacitance and reduced glass chip formation. The chip carrier includes a substrate having a central cavity for locating an integrated circuit die, an inner channel and an outer channel, adhesive glass located in the channels and overflowing above the substrate surface, a leadframe mounted on the substrate having a plurality of leads embedded in the adhesive glass overflow and coplanarly resting on the substrate, the leads extending from beyond the substrate periphery inward to near the cavity rim, and a thin layer of sealing glass extending from the periphery of the substrate over the outer channel for hermetically sealing the chip carrier.

Abstract: In a tightly coupled communication scheme based on a common shared resource circuit and adapted particularly to a multiprocessing system having 2.sup.N CPUs, a method of accessing data in a shared resource register. An instruction issue circuit reads a semaphore bit in a local control circuit. If the bit is clear, the next instruction issues. If, however, the bit is set, a branch is taken and instructions are executed starting at the branch address.

Abstract: An optimization method to be carried out within a digital computer under programmed control for eliminating or removing from a loop body alternate exit tests substantially of the form .alpha.i+.beta.cond.phi., where .alpha., .beta. and .phi. are loop invariant expressions, i is the innermost loop index variable, and cond is one of the relational operators (=,.noteq.,>,.gtoreq.,<,.ltoreq.). Each alternate exit test is compared to a list of elimination conditions. If an alternate exit test matches one of the elimination conditions, it is eliminated entirely from the loop body. If the alternate exit test cannot be eliminated, it is then compared to a list of restriction conditions. If the alternate exit test matches one of the restriction conditions, the loop index upper bound is modified if necessary and the alternate exit test is moved from inside to outside of the loop body. The resulting altered loop body is near optimum in terms of both the storage area utilized and the program execution time.

Abstract: A method for simultaneously manufacturing metallized carriers from wafer-shaped substrates is described, wherein such wafer-shaped substrates permit the use of standard IC fabrication apparatus and methods. As a result, very thin and finely dimensioned traces can be deposited. Thin-film manufacturing techniques are used to create the high-density traces on the surface of the chip carriers, thereby permitting direct connections from the IC to the periphery of the carrier without the need for vias. A lid hermetically seals and protects the package. The traces are comprised of a plurality of metals to facilitate bonding, each of the metals homogeneous for a portion of the trace. One metal portion of the trace is of a type compatible with an IC chip placed in the carrier. Another metal portion of the trace is of a type compatible with a trace on a printed circuit board. A metal barrier is interposed between the metals to prevent metal diffusion from one metal to an adjoining portion of another metal.

Abstract: Utilization circuits, such as logic chip circuits, are prevented from receiving the initial one or more pulses of a train of clock pulses produced after the master system clock is started, while the pulses of that train occurring thereafter are coupled to the utilization circuit. This prevents the skew usually present between the initial pulses of the train relative to the subsequent train pulses from adversely effecting operation of the utilization circuits. This clock swallowing preferably blocks a certain predetermined number of initial clock pulses from reaching the rest of the circuitry, although the system is adaptable to allow preselection of the number of such swallowed pulses.

Abstract: Improved performance is obtained in computers of the type having vector registers which communicate with one or more functional units and common memory. As elements of a vector are read from a vector register for transmission to common memory or as operands to a functional unit, the vector register immediately becomes available to receive and store elements of a vector from common memory or a functional unit. The element-by-element storing takes place simultaneously with the element-by-element reading, and trails the reading by at least one element so as to not overwrite elements yet to be read. Through the use of this technique a vector register can be loaded with a vector for a subsequent operation without having to wait for the completion of the previous operation which uses the same vector register.

Abstract: A modular input-output subsystem for a supercomputer is disclosed. Peripheral devices are coupled to the system through channel adaptor interfaces, while communication with the CPU is through high speed data channels. A memory buffer is provided to buffer data transfers between the peripherals and the Central Processing Units (CPUs) and the Solid State Storage Devices (SSDs).

Abstract: The present invention discloses a method and apparatus for conductively transferring heat away from electrical devices located on daughter boards attached to mother boards. The preferred method involves the steps of conductively transferring heat from each electrical device to a conductive layer located within the daughter board, transferring heat from the conductive layer within the daughter board to a conductive structure located on the surface of the daughter board, and transferring heat from the conductive structure to a cooling surface located on the cold plate. The preferred apparatus includes a mother board, a cold plate adjacent the mother board and attached to the mother board, a daughter board with an electrical device attached thereto, the daughter board attached to the mother board opposite the cold plate. The daughter board lies in a plane which is adjacent and substantially parallel to the plane of the mother board.

Abstract: On a tightly coupled multiprocessor computer system, the multiple parallel regions of a multithreaded applications program can execute simultaneously as multiple threads on a plurality of processors. Furthermore, a plurality of multithreaded programs may run simultaneously. The current invention uses an efficient system to schedule and reschedule processors to run these multiple threads. Scheduling is integrated at two levels: at the first level, processors are assigned processes. At the next level, processes are assigned threads. Increased efficiency is achieved by this integration and also by the formation of processes with destructible context. It makes use of shared storage to indicate the process request level and the control state for each parallel region.

Abstract: An alignment fixture for use in sealing integrated circuit packages including a body having rectangular alignment cavities therein for receiving components of integrated circuit packages. The body is inclined at an angle relative to a horizontal reference plane. The rectangular alignment cavities are rotated at 451/2 angle relative to a longitudinal axis of the body.

Abstract: The skew of a circuit within a clock pulse distributing network is determined by establishing a closed loop circuit including the circuit under test. A sampling period is established such as by a counter actuated by the clock pulses. During that sampling period, the number of pulses recurring within the closed loop circuit are counted in yet another counter. The count is then useful not only to indicate the magnitude of the circuit skew but also allows optimization of the delay introduced to the circuit under test during normal operation. The skew is thus determined dynamically under typical machine environment situations.

Abstract: Maintenance modes of operation of a multiprocessing vector supercomputer system are disclosed. The modes allow diagnostics to run on a failed portion of the system while simultaneously allowing user tasks to run in a degraded performance mode. This is accomplished by assigning a processor or a group of processors to run diagnostics on an assigned portion of memory, while the operating system and user tasks are run in the remaining processors in the remaining portion of memory. In this manner, the diagnostics can isolate the problem without requiring complete shut down of the user task, while at the same time protecting the integrity of the operating system. The result is significantly reduced preventive maintenance down time, more efficient diagnosis of hardware failures, and a corresponding increase in user task run time.

Abstract: An improved solid state storage device (SSD) with memory organized into a plurality of groups, each group including a plurality of ranks, and each rank having at least two banks sharing a bidirectional data bus. A matrix reorder circuit is used to distribute data across individual memory components in a way that prevents multibit uncorrectable or undetectable errors due to the failure of a single memory component. The matrix reorder circuit is used for both reading and writing data, and operates on a stream of pipelined data of arbitrary length.

Abstract: An air distribution system for electronic components utilizes an air supply unit with a silencer unit. The silencer unit attenuates sound associated with the air unit blowers with inlet and discharge silencers. The blowers have check valves which provide for isolating each blower for continued operation even with one blower. The cooling air is transported to a circuit board module stack from the blowers through ducts and a bank of rod valves. The valves allow maximum air flow to the modules with minimum resistance. The ducts have a flexible portion which have quick disconnects and act to isolate the modules from vibrations and static. The modules utilize channels in an air plate with different sized baffles to provide even distribution of cooling air to the printed circuit boards.

Abstract: In a cooling system, an air manifold provides an equalized static pressure so that the air manifold evenly distributes air in a uniform basis without varying static pressures and volumes at each chip site on a printed circuit board. The air manifold is also distributes this air at the lowest possible volume so that the pumping energy required and the associated pumping noise are minimized.

Abstract: Clock pulses from a master oscillator are distributed in a multiprocessor computer system so that they arrive at a large number of utilization points located in operating clusters of modules within extremely tight time tolerances of each other. The delays associated with each component, electrical or optical connection, cable or the like are determined by direct measurement or by using known standard characteristics. A time delay budget for each complete clock pulse path from the point of initial divergence from the master clock source to the final chip delivery point is logged and summed. Components capable of introducing predetermined amounts of time delay are incorporated in some or all clock pulse paths. These components are adjusted so as to balance out the differences determined from the clock path budgets. The clock paths are implemented in electrical components either alone or in combination with optical components, or in substantially all optical configurations.

Abstract: A method of manufacturing interconnect bumps on electrical connectors is disclosed. The interconnect bumps are formed with mechanically interlocking structure which allows the bumps to reach a height substantially greater than prior art bumps, while remaining structurally intact. The interconnect bumps are formed using standard photolithography techniques to form the bumps in multiple interlocking portions to achieve a structurally superior interconnect bump.