Abstract: The present invention provides a circuit for distributing data from a number of individual memory cells in a memory array to a common output. The present invention uses a multi-bit counter to distribute a timing signal to a number of sense amplifier blocks. Each of the sense amplifier blocks receives both a data input signal from the memory array and the timing signal at all times. When a particular timing signal is present at a sense amplifier, the output signal containing a fixed width data word is received from the corresponding memory array and is presented to the output. The present invention reduces the number of internal signal lines necessary to implement the control function and allows for easy modification to read multiple width words from the memory array.

Abstract: Method and apparatus for controlling an output transistor in an output driver circuit. In one embodiment of the invention, an input signal is routed to a first gate body which is disposed over a first channel region in a substrate. The first gate body has a first resistance to the input signal and delays the input signal through the first gate body to provide a delayed input signal. This delayed input signal is routed to a second gate body which is disposed over a second channel region in the substrate. The first gate body is coupled to the second gate body to provide the delayed input signal to the second gate body. According to one embodiment of the invention, the transistor includes the first gate body coupled to an input signal and coupled to the second gate body to receive the input signal through the first resistance of the first gate body.

Abstract: A method and apparatus for reducing noise in a memory bit-line pull-up circuit. The memory bit-line pull-up circuit includes a first reference line, a second reference line, a first capacitor, a gating device, and a pull-down circuit. The circuit may further include a load transistor coupled between the first reference line and a first voltage conduit, which generally maintains the voltage on the first reference line at Vcc-Vt, and a second capacitor and the load transistor providing a pull-up path for the voltage on the first reference line when Vcc increases and the first capacitor. The pull-down circuit provides a pull-down path for the voltage on the first reference line when Vcc decreases. The first capacitor provides a pull-up path for the voltage on the second reference line. A first gating device couples a bit-line to the first reference line. The circuit further including a second gating device to couple a bit-line bar to the first reference line.

Abstract: A method and means for use when doing multiple products on an IC die and it becomes necessary to no-bond a control or address input thus requiring the connection of this IC input to a voltage of the proper polarity. In such a situation, an unused input pad is selectively bonded to a supply leadframe finger and connected to suitable logic to pull the unconnected IC input to the proper voltage. An embodiment whereby problems with noisy input voltages can be readily overcome is also described.

Abstract: A method and apparatus for writing data onto the read bitline when a FIFO buffer memory is nearly empty that includes circuitry detecting when a memory is nearly empty, when the read pointer and the write pointer are on the same line with the read pointer behind the write pointer. Another circuit writes data onto the read bitline as the data is written into the buffer memory.

Abstract: An equalizer circuit for equalizing waveform distortion of a signal that propagates through a lossy transmission cable connected between a receiver and a transmitter, the equalizer circuit including a plurality of equalizer units which are connected in series with one another and a plurality of taps, each tap providing a different equalized representation of a signal being transmitted through the transmission cable to which the equalizer circuit is connected, and a control circuit for determining the tap at which appears an equalized signal that exhibits minimum error relative to the transmitted signal, the determination being made by applying an envelope detector to each tap for obtaining low frequency envelope signals for the signal appearing at each tap and for comparing the low frequency envelope signals thus obtained with a common DC reference signal that is related to the ideal transmitted signal amplitude.

Abstract: A First-In-First-Out (FIFO) memory device having polled status flags to provide the status of the FIFO memory device when requested by an external source. The write pointer and the read pointer in the memory device specifies the memory location which is to be accessed during the next write operation or during the next read operation, respectively. The write pointer generates a value indicating the number of write operations that have been performed and the read pointer generates a value indicating the number of read operations that have been performed. In response to a polling signal from the external source, the FIFO memory device outputs the value indicating the number of locations that are currently written (i.e. used) or the value indicating the number of locations currently unwritten (i.e. available for use).

Abstract: An improved high-speed sense amplifier is disclosed for use in programmable logic devices (PLDs) and complex PLDs. The sense amplifier includes a transresistance amplifier portion that provides a voltage potential to a first node of a memory array, which defines a read product term line. The current drawn by the memory array will cause the output of the amplifier to change states once a predetermined current level is reached, the predetermined trip point indicating that at least one memory cell is conducting. The amplifier includes an n-channel MOS transistor having its drain connected between a second node of the memory array, and its source to ground. The gate of the n-channel transistor is connected to the read product line. The n-channel limits current through the memory array by raising the potential at the second node, thus reducing the voltage drop across the memory array.

Abstract: A rapid thermal anneal (RTA) process minimizes the intermixing of materials between a bump and a bonding pad so as to provide for a more reliable and durable interconnect between the bump and the bonding pad and so as to allow the probing of wafers prior to bumping. A barrier layer is formed over the bonding pads of devices formed over a semiconductor substrate. Bumps are then formed over the bonding pads and are annealed for a short time at a high temperature so as to soften the bumps for later assembly in a semiconductor package. As a result of this quick annealing process, the intermixing of materials between the bumps and the bonding pads is minimized. This is so despite any decreased step coverage of the barrier layer over probe marks on the bonding pads which resulted from testing the wafer. Accordingly, wafers may now be tested prior to bumping, thus saving the cost, time, and process steps typically incurred in bumping wafers having a zero or low yield of properly functioning semiconductor devices.

Abstract: A voltage output clamp circuit includes a reference voltage generator, a switched differential operational amplifier, and an output driver circuit. The reference voltage generator has a first input coupled to a first reference voltage and a second input coupled to a second reference voltage. An output of the reference voltage generator is coupled to a first input of the switched differential operational amplifier. The output of the operational amplifier is coupled to an input of the output driver circuit and an output of the output driver circuit is coupled to a second input of the operational amplifier, providing a feedback path. The voltage output clamp circuit may further include a first NAND gate receiving a first logical signal and an output enable signal and providing an output. The output of the first NAND gate may be coupled to an input of a first transistor which is arranged to provide an electrical path between the first reference voltage and the operational amplifier.

Abstract: A delay lock loop having an improved delay element which results in a two-fold improvement in the operation of the delay lock loop. Firstly, it guarantees that the phase detector portion of the delay lock loop will yield the correct phase differential. Secondly, it eliminates the possibility of a harmonic lock condition from occurring.

Abstract: The present invention provides a circuit and method for manipulating the least significant bit (LSB) of the read and write count signal to generate a glitch free mutually non-exclusive decoder output. The present invention can be used to generate a logic to eliminate glitches in the inputs to a full/empty flag generator, an almost full/almost empty flag generator or a half-full/half-empty flag generator. The circuit can be extended to generate the logic to eliminate glitches in either direction as the count signals move across a boundary change in a half-full flag generation circuit.

Abstract: A programmable circuit apparatus having a programmable circuit and an input/output circuit with a first terminal is provided. The programmable circuit apparatus includes a programming circuit, with a bus junction, for programming the programmable circuit. The programmable circuit apparatus further includes an isolation circuit having an isolation input, coupled to the first terminal, and an isolation output, coupled to the bus junction of the programming circuit. The isolation circuit further has an isolation control gate which can receive a control signal and in response to that signal, the control gate controllably couples the isolation input to the isolation output. The programmable circuit apparatus also includes an apparatus for testing the routing, the programming circuitry, and the programmable circuit with a minimal impact on the performance of the programmable circuit.

Abstract: The present invention relates to a solid-state bi-stable circuit functioning as a six-bulk transistor static memory cell, the circuit comprising a plurality of bitlines and at least a first and second reference line, all of which are positioned in parallel with a plurality of wordlines. The circuit further comprises a plurality of transistors including a first and second load transistor, a first and a second pull-down transistor and a first and a second access transistor, in which each of the plurality of transistors includes a gate, source and drain. The gates of the plurality of transistors are positioned in parallel to minimize area usage.

Abstract: A method and apparatus that controls and modulates the amount of hysteresis in a buffer in response to changes in operating conditions. The buffer comprises a first stage switching element and a hysteresis control element. The first stage switching element is configured to have a DC voltage trip point. As an input voltage, transitioning from a first state to a second state, is applied to the first stage switching element, the first stage switching element transitions as the input voltage reaches the DC voltage trip point. The transition of the first stage switching element enables the hysteresis control element to provide a feedback path biasing the first stage switching element. Consequently, as the input voltage transitions from the second logic level to the first logic level, the first stage switching element transitions at a voltage level offset from the DC trip point to provide hysteresis in the buffer.

Abstract: A high speed ratio CMOS logic structure includes a static PMOS pullup transistor connected to an output node, and a plurality of NMOS pulldown transistors, connected in parallel, to the output node and which collectively define a pulldown circuit. The pullup transistor is biased using a reference voltage to define a static pullup strength for the logic structure. The pulldown strength of the pulldown circuit is also fixed. The combination of the pullup transistor, and the pulldown transistors define an N input NOR gate. The logic structure, however, further includes a feedback logic circuit, formed by a pair of inverters connected in series coupled to the output node to sense a current logic state of the output node. The feedback logic circuit generates an enable signal that is provided to a second, dynamic PMOS transistor connected in parallel with the static pullup PMOS transistor.

Abstract: A lithographic patterning process uses multiple exposures to provide for relatively reduced pitch for features of a single patterned layer. A first imaging layer is exposed to radiation in accordance with a first pattern and developed. The resulting patterned layer is stabilized. A second imaging layer is subsequently formed to surround the first patterned layer, exposed to radiation in accordance with a second pattern, and developed to form a second patterned layer. As the first patterned layer has been stabilized, the first patterned layer remains with the second patterned layer to produce a single patterned layer. For another embodiment, a single imaging layer is patterned by exposure to radiation in accordance with two separate patterns. An exposed portion of the imaging layer is suitably stabilized to withstand subsequent lithographic process steps.

Abstract: A memory device including a memory array and a series of sense amplifiers coupled to the memory array. The memory array includes numerous memory cells. A clock transmission line receives a clock signal and forms a clock word line within the memory device. A circuit is coupled to the clock transmission line and includes at least one transistor device coupled to the clock transmission line to receive the clock signal. The circuit also includes a clock output coupled to one of the sense amplifiers.

Abstract: A disposable post process for contact openings to interconnect material of reduced geometry and no enlarged landing pads is disclosed. A layer of material is formed over interconnect regions on a semiconductor wafer and subsequently patterned into posts which define the location and shape of openings to be formed in a subsequently formed planar layer. After a layer is formed to surround the posts, the posts are removed to create openings in the layer above underlying interconnect regions. These openings may then be used to form suitable contacts to the interconnect regions.

Abstract: An anchor structure placed in an open field in corner areas of the semiconductor die and along die edges for preventing cracks in the die. In the corner areas, the anchor structure is placed perpendicular to a resultant vector force, which is approximately at a 45.degree. angle to an imaginary horizontal line passing through the die. This perpendicular placement of the anchor structure more uniformly distributes the stresses along the anchor preventing corner cracks in the die. Along the die edges, the anchor structures are placed approximately perpendicular to the resultant vector forces that impinge the die edges.