Patents Assigned to Cypress Semiconductor
  • Patent number: 10990560
    Abstract: A USB-C controller, disposed on an integrated circuit (IC), comprises a first pair of terminals to communicate with a first communication protocol that is other than USB, a second pair of terminals to communicate with a second communication protocol that is other than USB, and a third pair of terminals, each of which is to be coupled to a corresponding SBU1 terminal or SBU2 terminal of a Type-C receptacle. The USB-C controller further includes: a multiplexer to selectively couple the first pair of terminals to the third pair of terminals and the second pair of terminals to the third pair of terminals: and logic to control the multiplexer according to a mode enabled within a configuration channel (CC) signal.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: April 27, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Arun Khamesra, Anup Nayak, Partha Mondal, Hemant Prakash Vispute, Ravi Konduru
  • Patent number: 10993074
    Abstract: A passive entry, passive start (PEPS) application is described, wherein a number of sensors are configured with wireless communication protocol information for wireless communication between a master device and a BLE hub. The sensors eavesdrop signals from the master device to the BLE hub while not in operative communication with the master device. Eavesdropped signals are processed to determine and calculate position-related information, such as phase and magnitude of the wireless signals received at multiple antennas of the sensors, angle-of-arrival (AoA), and distance or position of the master device relative to the sensors, individually or as a system. Power management techniques for a PEPS system are also described.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: April 27, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Tessa Ronan, Victor Simileysky, Walter James Wihardja, Kiran Uln
  • Patent number: 10984815
    Abstract: Techniques for non-linear acoustic echo cancellation are described herein. In an embodiment, a system comprises a loudspeaker, a microphone array, a spatial filtering logic with a spatial filter, an acoustic echo canceller (AEC) logic and an adder logic block. The spatial filtering logic is configured to generate a spatially-filtered signal by applying the spatial filter using a reference signal sent to the loudspeaker and a multi-channel microphone signal from the microphone array. The generated spatially-filtered signal carries both linear echo and non-linear echo that are included in the multi-channel microphone signal. The AEC logic is configured to apply a linear adaptive filter using the spatially-filtered signal to generate a cancellation signal that estimates both the linear echo and the non-linear echo of the multi-channel microphone signal. The adder logic block is configured to generate an output signal based on the cancellation signal.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: April 20, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Ashutosh Pandey, Ted Wada
  • Patent number: 10979120
    Abstract: Implementations disclosed describe systems and methods to optimize delivery of channel state information in wireless networks. In one implementation, a beamformee device may comprise a plurality of antennas, to receive radio frequency signals, a radio circuit coupled to the plurality of antennas, the radio circuit to generate strength indicators of the received radio frequency signals, and a processor to determine, based on the strength indicators, a first set of feedback parameters characterizing signal transmission received by each of the plurality of antennas, generate a sparse set of feedback parameters from the first set of feedback parameters, generate a second set of feedback parameters with elements of the sparse set that exceed a threshold value, and cause the radio circuit to transmit the second set of feedback parameters.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: April 13, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventor: Prasanna Kumar Sethuraman
  • Patent number: 10978127
    Abstract: Semiconductor memory devices and methods of operating the same are provided. The method of operation may include the steps of selecting a ferroelectric memory cell for a read operation, coupling a first pulse signal to interrogate the selected ferroelectric memory cell, the selected ferroelectric memory cell outputting a memory signal to a bit-line in response to the first pulse signal, coupling the memory signal to a first input of a sense amplifier via the bit-line, electrically isolating the sense amplifier from the selected ferroelectric memory cell, and enabling the sense amplifier for sensing after the sense amplifier is electrically isolated from the selected ferroelectric memory cell. Other embodiments are also disclosed.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: April 13, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Alan D. DeVilbiss, Jonathan Lachman
  • Publication number: 20210104533
    Abstract: A semiconductor device and method of making such device is presented herein. The method includes disposing a gate layer over a dielectric layer on a substrate and further disposing a cap layer over the gate layer. A first transistor gate is defined having an initial thickness substantially equal to a combined thickness of the cap layer and the gate layer. A first doped region is formed in the substrate adjacent to the first transistor gate. The cap layer is subsequently removed and a second transistor gate is defined having a thickness substantially equal to the thickness of the gate layer. Afterwards, a second doped region is formed in the substrate adjacent to the second transistor gate. The first doped region extends deeper in the substrate than the second doped region, and a final thickness of the first transistor gate is substantially equal to the thickness of the second transistor gate.
    Type: Application
    Filed: September 8, 2020
    Publication date: April 8, 2021
    Applicant: Cypress Semiconductor Corporation
    Inventors: Chun Chen, Mark Ramsbey, Shenqing Fang
  • Patent number: 10972973
    Abstract: Two methods for energy-efficient idle listening enhancement for WLAN systems are provided. The first method performs a change of operation of a station (STA) from an active mode to an idle listening mode without notifying the change to an access point (AP) associated with the STA. In the idle listening mode, the AP may transmit frames to the STA using a higher bandwidth, but the STA can only sense channels in a lower bandwidth to save energy. The second method transmits a frame to the AP associated with the STA to notify the AP the change of operation of the STA from the active mode to the idle listening mode. In the idle listening mode, the AP may transmit frames to the STA using the lower bandwidth, and the STA can only sense channels in the lower bandwidth to save energy.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: April 6, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Kamesh Medapalli, Rajendra Kumar Gundu Rao, Xianmin Wang, Sangho Seo
  • Patent number: 10972886
    Abstract: An example method of operating a device includes using a switching circuitry to a first subset of antennas from an antenna cluster, using the first subset of antennas to receive a first Bluetooth signal, generating a first directional value of the first Bluetooth signal, using a processing element to evaluate at least one antenna of the antenna cluster based at least partly on the first directional value, selecting a second subset of antennas based on evaluation, using the second subset of antennas to receive a second Bluetooth signal, and generating a second directional value of the second Bluetooth signal. Other embodiments of the device and operations thereof are also disclosed.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: April 6, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventor: Victor Simileysky
  • Patent number: 10969249
    Abstract: A method, apparatus, and system use logic circuitry arranged within an integrated circuit to: convert a self capacitance of a first sensor element arranged within the integrated circuit to a digital value, and apply a signal to an output pin of the integrated circuit based on the self capacitance.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: April 6, 2021
    Assignee: Cypress Semiconductor Coproration
    Inventors: Rajagopal Narayanasamy, Mahadevan Krishnamurthy Narayana Swamy, David G. Wright, Steve Kolokowsky
  • Patent number: 10971990
    Abstract: Techniques for avoiding false negative sense (NSN) detection in a flyback AC-DC converter are described herein. In an example embodiment, a secondary side controller of the AC-DC converter comprises a frequency detector, a negative sense detector, and control logic. The frequency detector is configured to determine a frequency of an input signal from the drain node of a synchronous rectifier (SR) circuit on the secondary side of the AC-DC converter. The negative sense detector is configured to determine a negative voltage of the input signal. The control logic is configured to: enable the negative sense detector, when the frequency of the input signal rises above a frequency threshold value; and turn on the SR circuit to transfer power to the secondary side of the AC-DC converter, when the negative voltage of the input signal falls below a voltage threshold value.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: April 6, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Karri Rajesh, Arun Khamesra
  • Publication number: 20210099961
    Abstract: Disclosed are methods and systems for tailoring the transmit power of a wireless device to the parameters of the device such as the process split, voltage, and temperature. The device may identify one or more parameters of the device such as identifying the process split, or sensing the operating voltage or temperature. The device may determine an updated transmit power based on the known parameter values identified and any unknown parameter values. The updated transmit power is determined to be a maximum transmit power that meets one or more target transmit metrics, such as EVM and spectral mask, when the device transmits based on the known parameter values and across a range of variations of the unknown parameter values. The device may adjust its transmit power based on the updated transmit power periodically.
    Type: Application
    Filed: September 27, 2019
    Publication date: April 1, 2021
    Applicant: Cypress Semiconductor Corporation
    Inventors: Ayush Sood, Kamesh Medapalli, Rajendra Kumar Gundu Rao, Patrick Cruise
  • Publication number: 20210096164
    Abstract: One embodiment includes and I/0 bus including a signal line coupled to a signal source and multiple line switches, each line switch to couple a corresponding I/0 port to the signal line. Switch logic coupled to the I/0 bus may programmatically switch the multiple line switches to couple at least one of the signal source and measurement circuitry to the respective I/0 port.
    Type: Application
    Filed: August 13, 2020
    Publication date: April 1, 2021
    Applicant: Cypress Semiconductor Corporation
    Inventor: Dennis R. Seguine
  • Publication number: 20210098015
    Abstract: Techniques for non-linear acoustic echo cancellation are described herein. In an embodiment, a system comprises a loudspeaker, a microphone array, a spatial filtering logic with a spatial filter, an acoustic echo canceler (AEC) logic and an adder logic block. The spatial filtering logic is configured to generate a spatially-filtered signal by applying the spatial filter using a reference signal sent to the loudspeaker and a multi-channel microphone signal from the microphone array. The generated spatially-filtered signal carries both linear echo and non-linear echo that are included in the multi-channel microphone signal. The AEC logic is configured to apply a linear adaptive filter using the spatially-filtered signal to generate a cancellation signal that estimates both the linear echo and the non-linear echo of the multi-channel microphone signal. The adder logic block is configured to generate an output signal based on the cancellation signal.
    Type: Application
    Filed: September 27, 2019
    Publication date: April 1, 2021
    Applicant: Cypress Semiconductor Corporation
    Inventors: Ashutosh Pandey, Ted Wada
  • Publication number: 20210097254
    Abstract: A circuit, system, and method for measuring or detecting pressure or force of a fingerprint on an array of electrodes is described. Pressure or force may be measured or detected using a processed image of the fingerprint, or by measurement of capacitance of deformed variable capacitors.
    Type: Application
    Filed: August 20, 2020
    Publication date: April 1, 2021
    Applicant: Cypress Semiconductor Corporation
    Inventors: Andriy Ryshtun, Viktor Kremin
  • Publication number: 20210091654
    Abstract: Techniques for avoiding false negative sense (NSN) detection in a flyback AC-DC converter are described herein. In an example embodiment, a secondary side controller of the AC-DC converter comprises a frequency detector, a negative sense detector, and control logic. The frequency detector is configured to determine a frequency of an input signal from the drain node of a synchronous rectifier (SR) circuit on the secondary side of the AC-DC converter. The negative sense detector is configured to determine a negative voltage of the input signal. The control logic is configured to: enable the negative sense detector, when the frequency of the input signal rises above a frequency threshold value; and turn on the SR circuit to transfer power to the secondary side of the AC-DC converter, when the negative voltage of the input signal falls below a voltage threshold value.
    Type: Application
    Filed: December 5, 2019
    Publication date: March 25, 2021
    Applicant: Cypress Semiconductor Corporation
    Inventors: Karri Rajesh, Arun Khamesra
  • Publication number: 20210089100
    Abstract: A device includes a USB-C controller instantiated as a first integrated circuit that includes a first set of host terminals coupled to host controllers and a second set of terminals coupled to sets of D+/D? terminals of a type-C receptacle. A D+/D? multiplexer is to selectively couple the first set of host terminals to the second set of terminals. An electrostatic discharge (ESD) protection circuit is coupled between the D+/D? multiplexer and the second set of terminals. A charger detector circuit is coupled between a positive data system terminal and a negative data system terminal of the first set of terminals, the charger detector circuit to detect whether the second set of terminals is coupled to a USB charger through the type-C receptacle.
    Type: Application
    Filed: October 1, 2020
    Publication date: March 25, 2021
    Applicant: Cypress Semiconductor Corporation
    Inventors: Anup Nayak, Karri Rajesh, Hemant P. Vispute, Arun Khamesra
  • Publication number: 20210091823
    Abstract: A system made up of a first device which includes a communication interface and a processing device and a second device which includes a touch sensor assembly and a controller, where the controller uses the touch sensor assembly to communicate with the processing device through a capacitor that is jointly formed by the touch sensor assembly and a conductive portion of the communications interface.
    Type: Application
    Filed: August 12, 2020
    Publication date: March 25, 2021
    Applicant: Cypress Semiconductor Corporation
    Inventor: David G. Wright
  • Publication number: 20210091675
    Abstract: A synchronous switching scheme with adaptive slew control in order to adiabatically charge and discharge a capacitor to recycle charge and generate a boosted voltage on the gate of the synchronous rectifier field effect transistor (FET) is described. In one embodiment, an apparatus includes a synchronous rectifier FET coupled to a transformer, and a secondary-side controller coupled to the synchronous rectifier FET. The secondary-side controller includes a synchronous rectifier gate driver (SRGD) coupled to a gate of the synchronous rectifier FET. The SRGD is to drive the synchronous rectifier FET using the capacitor and an adaptive slew rate, and to adiabatically charge and discharge the capacitor.
    Type: Application
    Filed: December 19, 2019
    Publication date: March 25, 2021
    Applicant: Cypress Semiconductor Corporation
    Inventors: Karri Rajesh, Arun Khamesra
  • Publication number: 20210091867
    Abstract: Systems, methods, and devices detect variations in load impedances of wireless communications devices. Methods include determining a first distortion measurement of a transceiver based on a first comparison of a digital loopback path and a radio frequency (RF) loopback path, and determining a second distortion measurement of the transceiver based on a second comparison of the digital loopback path and the RF loopback path. Methods also include implementing, using a processor, a third comparison of the first distortion measurement and the second distortion measurement, and determining if there is a change in a load of the transceiver based on the third comparison.
    Type: Application
    Filed: September 24, 2019
    Publication date: March 25, 2021
    Applicant: Cypress Semiconductor Corporation
    Inventors: Vipul Kumar, Raghuram Kuchibhotla
  • Publication number: 20210091198
    Abstract: A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed.
    Type: Application
    Filed: September 30, 2020
    Publication date: March 25, 2021
    Applicant: Cypress Semiconductor Corporation
    Inventors: Shenqing Fang, Chun Chen, Unsoon KIM, Mark T. Ramsbey, Kuo Tung Chang, Sameer S. HADDAD, James Pak