Abstract: Controlling gate-source voltage with a gate driver in a secondary-side integrated circuit (C) controller for a secondary-controlled AC-DC converter is described. In an example embodiment, the gate driver is configured to programmably control the gate-source voltage and the slew rate of a secondary-side provider field effect transistor (FET) in the converter.

Abstract: Systems, methods, and apparatus cause a first wireless device to transmit to a plurality of locator devices, an extended signal including a first segment and second segment. The first segment includes an indication for each of the plurality of locator devices to listen for a change in the extended signal from the first segment to the second segment. The second segment includes an indication for each of the plurality of locator devices to rotate through a plurality of antennas to receive the second segment via the plurality of antennas. Responsive to the transmitting of the extended signal, receiving direction data from each of the plurality of locator devices.

Abstract: Apparatuses and methods of converting a capacitance measured on a sense element to a digital value are described. One apparatus includes a modulator having a modulator capacitor, a sense element selectively coupled in a feedback loop of the modulator to operate as a switching capacitor. The apparatus also includes a first switch coupled between a voltage source and a first node of the switching capacitor and a second switch coupled between the first node of the switching capacitor and a first node of the modulator capacitor. The switching capacitor provides a charge current to the modulator capacitor via the second switch. The modulator measures a capacitance of the sense element and converts the measured capacitance to a digital code representing the capacitance.

Abstract: A split gate device that includes a memory gate and a select gate disposed side by side, a dielectric structure having a first portion disposed between the memory gate and a substrate and a second portion disposed along an inner sidewall of the select gate to separate the select gate from the memory gate, and a spacer formed over the select gate along an inner sidewall of the memory gate. Other embodiments of embedded split gate devices including high voltage and low voltage transistors are also disclosed.

Abstract: A device can include a plurality of processing sources; a multiplexer (MUX) configured to assign read requests from the processing sources to predetermined time division multiplexer (TDM) command slots. A memory controller can generate nonvolatile memory (NVM) command and address data from read requests received from the MUX during the TDM command slots assigned to the read requests on a unidirectional command-address bus. The address data can include at least a bank address. The device can also receive read data on a unidirectional parallel data bus in synchronism with rising and falling edges of a received data clock. The read data can be received in TDM read slots having a predetermined order. A demultiplexer can provide the read data of each TDM read slot to one of the processing sources based on the TDM read slot position in the predetermined order. Related methods and systems are also disclosed.

Abstract: A nonvolatile memory device can include a serial port having at least one serial clock input, and at least one serial data input/output (I/O) configured to receive command, address and write data in synchronism with the at least one serial clock input. At least one parallel port can include a plurality of command address inputs configured to receive command and address data in groups of parallel bits and a plurality of unidirectional data outputs configured to output read data in parallel on rising and falling edges of a data clock signal. Each of a plurality of banks can include nonvolatile memory cells and be configurable for access by the serial port or the parallel port. When a bank is configured for access by the serial port, the bank is not accessible by the at least one parallel port. Related methods and systems are also disclosed.

Abstract: Example apparatus, systems and methods use a receiver of a first device to receive from a second device, radio frequency (RF) signals. Embodiments use a processor of the first device to determine, based on the RF signals, a set of angle-estimation values of an angle between a plurality of antenna elements of one of the first device and the second device and an antenna element of the other of the first device and the second device, and a set of confidence measurements. Each of the set of confidence measurements indicates a confidence of an angle-estimation value of the set of angle-estimation values.

Abstract: A touch screen display and corresponding devices and methods are disclosed, the touch screen display comprising a touchscreen having a plurality of capacitive sensors and a passive dial having one or more conductive elements, the passive dial mounted within an active area of the touchscreen such that the one or more conductive elements are proximate to the face of the touchscreen and move in conjunction with a rotation of the passive dial. The touch screen display may further include a touchscreen controller to detect an angle of the passive dial using conventional capacitive sensing techniques.

Abstract: A method includes receiving at a wireless access point a first probe request from a first client device requesting connection with the wireless access point via a first frequency band, queueing the first client device in response to an indication that the first client device supports connection via the second frequency band, and in response to receiving at the wireless access point a second probe request from the first client device requesting connection with the wireless access point via the second frequency band, establishing a connection between the wireless access point and the first client device using the second frequency band.

Abstract: A method can include, in response to receiving a read request at a memory controller, sending a read command and address values on a command address bus in synchronism with a clock. In response to the read command, receiving an uninterrupted burst of read data values on at least one parallel data bus, the burst of read data values having double date rate with respect to the clock, and receiving error correction code (ECC) values for the read data values in response to the same read command, the ECC values not being included in the burst of read data values being output on non-ECC input/outputs (I/Os); wherein the non-ECC I/Os are I/Os not assigned to ECC data according to a preexisting standards organization. Corresponding systems and devices are disclosed.

Abstract: A method can include, in an access point (AP) configured to control data transfers for associated stations (STAs) in time intervals, storing a unique identifier and quality-of-service (QoS) requirement for each STA of a first set in a nonvolatile memory of the AP. In response to a STA associating with the AP, if the associating STA is in the first set, allocating time for the STA in the time intervals to meet the QoS requirement of the STA without receiving transmitted QoS data from the STA, and if the associating STA is not in the first set, establishing a QoS for the STA having a lower priority than any associated STAs of the first set. Corresponding systems and devices are also disclosed.

Abstract: A secondary-side controller for an AC-DC converter that has a single synchronous rectifier sensing (SR_SNS) terminal, coupled to a synchronous rectifier (SR) of the AC-DC converter, and a voltage divider circuit coupled to the single SR_SNS terminal configured to provide signals to a sensing circuit. The voltage divider includes an active diode, an internal resistive element, and a switch, in which the active diode is configured to control the switch to enable or disable the internal resistive element based on a comparison result of a voltage at the single SR_SNS terminal and a reference voltage.

Abstract: An apparatus and method of measuring a collective capacitance on a group of capacitive sense elements from at least one of rows or columns of a capacitance sense array when in a first mode, and individually measuring capacitances on each of the rows and columns when in a second mode.

Abstract: An example method for estimating the angle-of-arrival (AoA) and other parameters of radio frequency (RF) signals that are received by an antenna array comprises: receiving a plurality of radio frequency (RF) signal power measurements by a plurality of antenna elements at a plurality of RF channels; computing, by applying a machine learning model to the plurality of RF signal power measurements, an estimated RF signal parameter value; and outputting the RF signal parameter value.

Abstract: An example method of estimating the angular resolution of antenna array comprises: receiving a plurality of values of magnitude and phase of a radio frequency (RF) signal for each antenna element of a plurality of antenna elements comprised by an antenna array; performing, by a machine learning model, a feature extraction operation to transform the plurality of values of magnitude and phase into a plurality of data points in a reduced-dimension space; clustering, by the machine learning model, the plurality of data points into a plurality of clusters; and computing, based on the clustered data points, an angular resolution value for the antenna array.

Abstract: A method can include storing first instruction data in a first region of a nonvolatile memory device; mapping addresses of the first region to predetermined memory address spaces of a processor device; executing the first instruction data from the first region with the processor device; receiving second instruction data for the processor device. While the first instruction data remains available to the processor device, the second instruction data can be written into a second region of the nonvolatile memory device. By operation of the processor device, addresses of the second region can be remapped to the predetermined memory address spaces of the processor device; and executing the second instruction data from the second region with the processor device.

Abstract: An example system and method monitor a wireless transmission medium for packets of a first protocol type with first communication circuits of a device while yielding the medium for communications of a second protocol type by second communication circuits of the device. Responsive to the first communication circuits detecting a packet of the first protocol type while the medium is yielded to the second communication circuits, the system and method requests access to the medium for the first communication circuits and in response to granted access to the medium, uses the first communication circuits to execute a data transmission operation according to the first protocol. Responsive to completing the data transmission operation by the first communication circuits the system and method yield the medium back to the second communication circuits.

Abstract: A system includes a transceiver configured to receive frequency dependent channel estimates or beamforming feedback in a multi-carrier, multi-antenna communication system, and a multi-layer perceptron feed forward neural network component, coupled with the transceiver, configured to estimate parameters of multipath reflections using representations of the channel estimates or beamforming feedback, and to generate transmission correction factors for the transceiver.

Abstract: In an example embodiment, a Universal Serial Bus Type-C (USB-C) cable comprises a respective integrated circuit (IC) controller, disposed at each end of cable, that is coupled to a respective VCONN line at that end of the cable. Each IC controller comprises a power rail, a VDDD terminal, a VBUS terminal, and a VCONN terminal that is coupled to the VCONN line at the respective end of the cable. The VDDD terminal, the VCONN terminal, and the VBUS terminal are coupled to the power rail. The power rail is coupled to internal circuits of the IC controller and is configured to provide operating power to the internal circuits of the IC controller from the its VCONN terminal.

Abstract: An AC-DC converter with secondary side control and synchronous rectifier (SR) architecture and method for operating the same are provided for reducing the cost, complexity and size of the converter while improving efficiency. In an example embodiment, an integrated circuit (IC) controller for the secondary side of the AC-DC converter comprises a zero-crossing detector (ZCD) block and a negative-sensing (NSN) block coupled to a terminal. The terminal is configured to receive an input signal from a drain node of a SR circuit on the secondary side of the AC-DC converter. The ZCD block is configured to determine when a voltage of the input signal reaches 0V. The NSN block is configured to determine a negative voltage of the input signal. An internal rectifier, coupled between the terminal and local ground, is configured to ensure that substantially no current flows through the terminal during operation of the ZCD block and the NSN block.