Abstract: An example embodiment comprises a method for fabrication of a non-volatile memory (NVM) device. An isolation structure is formed in a substrate between first and second locations for first and second NVM cells. A common charge trapping layer is formed as a continuous structure over the substrate, where a first portion of the charge trapping layer is disposed directly over the isolation structure and second portions of the charge trapping layer are disposed directly over the first and second substrate locations. Nitrogen doping of the first portion of the charge trapping layer is performed, where after the nitrogen doping is performed the first portion of the charge trapping layer includes a higher nitrogen concentration than the second portions. The first and second NVM cells are then formed over the first and second substrate locations, where the first and second NVM cells include the second portions of the charge trapping layer.

Abstract: An integrated circuit includes a processor coupled to a voltage bus of a cable and located within a universal serial bus (USB) compatible power supply device. A current sense amplifier (CSA) is coupled to a sense resistor to monitor a current of the voltage bus. A first comparator is coupled to the CSA and the processor and to trigger in response to detecting that a monitored current value from the CSA is greater than or equal to a first reference value, which includes a hysteresis offset value. An analog-to-digital converter (ADC) is coupled to the CSA and the processor. In response to detecting trigger of the first comparator, the processor is to trigger the ADC to measure an absolute current value of voltage bus, and cause an additional voltage, equal to a voltage drop across the cable based on the absolute current value, to be supplied to the voltage bus.

Abstract: An example system drives one or more transmit signals on first electrodes disposed in a first layer and propagating electrodes disposed in a second layer. The system measures a capacitance of sensors through a of second electrodes. Each second electrode crosses each first electrode to provide a plurality of discrete sensor areas, each discrete sensor area associated with a difference crossing and including a portion of at least one propagating electrode. Each second electrode is galvanically isolated from the first electrodes and the propagating electrodes.

Abstract: A memory string is disclosed including a plurality of core cells serially connected between a source select gate and a drain select gate along a channel. Each core cell includes a wordline separated from the channel by a stack of layers including a charge trapping layer. At least one of the source and drain select gates is a stacked select gate with a plurality of components, including a first component adjacent to the plurality of core cells and a second component separated from the core cells by the first component. The first component includes a wordline separated from the channel by a stack of layers including a charge trapping layer, and a distance between the wordline of the first component and the wordline of a first core cell in the plurality of core cells is substantially the same as distances between each wordline in the plurality of word core cells.

Abstract: Information associated with a plurality of components of a capacitance sensing system is received. Performance of the capacitance sensing system is simulated based on the information associated with the plurality of components of the capacitance sensing system. A set of configuration parameters for a capacitance sensing controller is generated without user intervention based on the simulated performance of the capacitance sensing system.

Abstract: Disclosed are methods and systems for a WLAN device operating on DFS channels to calibrate the PRI as well as delays between partial pulses of received radar pulses that are impaired due to channel and filtering effects. The calibrated PRI may approximate the PRI of the transmitted pulses. The calibrated delay between the partial pulses estimates the interval between two partial pulses that originally belong to the same transmitted pulse. Using the calibrated PRI and the calibrated delay between partial pulses, the WLAN device may reconstruct the original pulses from received impaired pulses even when the impaired pulses are delayed and partial pulses of the original pulses. The WLAN device may use the calibrated results to correct the shortened PW and varying PRI of the impaired pulses to restore the partial pulses to their full PW with a relatively uniform PRI, increasing the probability of detecting the radar signals.

Abstract: An example system and method operate a wireless device in a first mode with power to operate a communication resource of the wireless device at a first level. While operating the wireless device in the first mode, the system and method evaluates an attribute in a first portion of sensor data. Responsive to the evaluation of the attribute, the system and method transitions to the wireless device to operate in a second mode with power to operate the communication resource at a second level. The system and method use the communication resource to communicate packets via a wireless connection.

Abstract: Communicating fault indications between primary and secondary controller in a secondary-controlled flyback converter is described. In one embodiment, an apparatus includes a primary-side field effect transistor (FET) coupled to a flyback transformer coupled to the primary-side FET, and a primary-side controller coupled to the flyback transformer. The primary-side controller is configured to receive a signal from a secondary-side controller across a galvanic isolation barrier, apply a pulse signal to the primary-side FET in response to the signal to turn-on and turn-off the primary-side FET, communicate information to the secondary-side controller across the flyback transformer by varying a first pulse width of the pulse signal to a second pulse width and applying the pulse signal with the second pulse width to the primary-side FET.

Abstract: A method can include receiving frequency hop configuration data for a first wireless communication protocol via a second wireless communication protocol in second communication circuits; and configuring first communication circuits to communicate according to the first communication protocol with frequency hopping indicated by the frequency hop configuration data; wherein the first communication circuits and second communication circuits are formed in a same combination device. Related devices and systems are also disclosed.

Abstract: An electronic device includes a first switch configured to connect a first sideband use (SBU) terminal of a Universal Serial Bus Type-C (USB-C) controller to a first SBU terminal of a USB-C receptacle. The electronic device also includes a second switch configured to connect a second sideband use (SBU) terminal of the USB-C controller to a second SBU terminal of the USB-C receptacle. The electronic device further includes a voltage protection circuit configured to deactivate one or more of the first switch and the second switch when a voltage exceeding a predetermined threshold is detected. The voltage protection circuit includes a first set of diodes coupled to the first SBU terminal of the USB-C controller and a second set of diodes coupled to the second SBU terminal of the USB-C controller.

Abstract: Disclosed are methods and systems for a WLAN device operating on DFS channels to calibrate the PRI as well as delays between partial pulses of received radar pulses that are impaired due to channel and filtering effects. The calibrated PRI may approximate the PRI of the transmitted pulses. The calibrated delay between the partial pulses estimates the interval between two partial pulses that originally belong to the same transmitted pulse. Using the calibrated PRI and the calibrated delay between partial pulses, the WLAN device may reconstruct the original pulses from received impaired pulses even when the impaired pulses are delayed and partial pulses of the original pulses. The WLAN device may use the calibrated results to correct the shortened PW and varying PRI of the impaired pulses to restore the partial pulses to their full PW with a relatively uniform PRI, increasing the probability of detecting the radar signals.

Abstract: An overlaid erase block (EB) mapping scheme for a flash memory provides efficient wear-leveling and reduces mount operation latency. The overlaid EB mapping scheme maps a first type of EB onto one of a plurality of physical erase blocks, in a corresponding portion of the flash memory. The first type of EB includes a plurality of pointers. The overlaid EB mapping scheme also maps each of second and third types of EBs onto one of the physical EBs that is not mapped to the first type of EB. The second type of EBs store system management information and the third type of EBs store user data. When the flash memory is started up, the overlaid EB mapping scheme scans the corresponding portion to locate the first type of EB, locates the system EBs using the pointers, and locates the data EBs using the system management information.

Abstract: In an example embodiment, a method comprises: forming first spacers adjacent to a memory cell formed on a substrate, each of the first spacers being formed in direct contact with the substrate, where forming the memory cell includes forming a control gate electrode and a tunnel oxide layer over the substrate and subsequently etching completely at least the control gate electrode and the tunnel oxide layer that are disposed beyond the memory cell; forming an interlayer dielectric layer over the memory cell and the first spacers; forming a contact hole through the interlayer dielectric layer to at least reach the substrate; subsequent to forming the contact hole, forming a second spacer adjacent to one of the first spacers, where a height of the second spacer is greater than a height of the first spacers, the second spacer substantially contacting the substrate and the interlayer dielectric layer; and forming a contact in the contact hole.

Abstract: A system includes a primary field effect transistor (FET) coupled to a primary winding on a primary side of an alternating current-to-direct current (AC-DC) converter. The system also includes a gate driver, coupled to the primary FET, that is to, in response to a signal received from a startup controller of the AC-DC converter, turn on the primary FET. The gate driver includes a voltage bias p-type metal-oxide-semiconductor (VBP) buffer coupled between an external supply voltage and a VBP portion of driving chain circuitry, the driving chain circuitry to drive a gate of the primary FET. The gate driver also includes a voltage bias n-type metal-oxide-semiconductor (VBN) buffer coupled between a VBN regulator, which generates an internal supply voltage, and a VBN portion of the driving chain circuitry.

Abstract: A wireless communication device and method for operating the same for mitigating interference in a wireless communication network are provided. Generally, the method includes sensing with the wireless communication device pulses of electromagnetic radiation recurring within a band of frequencies used by the device for communication of signals, identifying the pulses as interference, and determining a number of frequencies of the interference within the band of frequencies used by the wireless communication device. Next, a sensitivity of the wireless communication device is reduced upon sensing one of the pulses and repeated at a frequency corresponding to the frequency of the interference. Thus, a spectrum of electromagnetic radiation around the wireless communication device is perceived by the device as free of interference, enabling it to transmit and/or receive more often. Other embodiments are also disclosed.

Abstract: Techniques for acoustic echo cancellation are described herein. In an example embodiment, a system comprises a speaker, a microphone array with multiple microphones, a beamformer (BF) logic and an acoustic echo canceller (AEC) logic. The speaker is configured to receive a reference signal. The BF logic is configured to receive audio signals from the multiple microphones and to generate a beamformed signal. The AEC logic is configured to receive the beamformed signal and the reference signal. The AEC logic is also configured to compute a vector of bias coefficients multiple times per time frame, to compute a background filter coefficient based on the vector of bias coefficients, to apply a background filter to the reference signal and the beamformed signal based on the background filter coefficient, to generate a background cancellation signal, and to generate an output signal based at least on the background cancellation signal.

Abstract: A driver circuit and corresponding methods and systems are disclosed, the driver circuit comprises a signal generation circuit to generate a linearly varying signal at a first node based on a clock signal and an output transistor to receive the linearly varying signal and output a drive signal to a bus. A buffer amplifier is coupled between the first node and a gate of the output transistor to disable the gate capacitance of the output transistor. The driver circuit further comprises a capacitor coupled between the first node and a feedback node of the driver circuit such that the Miller effect occurs at the capacitor and a slew rate for the drive signal is generated at the feedback node.

Abstract: According to embodiments, methods, devices and systems can include monitoring all of a first channel for a first monitoring period. After the first monitoring period, monitoring at least one narrow band for at least a first narrow band signal. In response to detecting the first narrow band signal, establishing a network connection over the narrow band, wherein the at least one narrow band has a frequency range less than one half that of the first channel.

Abstract: Controlling an active clamp field effect transistor (FET) in a secondary-controlled active clamp converter is described. In one embodiment, an apparatus includes a primary-side FET coupled to a transformer, a secondary-side FET coupled to the transformer, and an active clamp FET disposed on a primary side of the transformer. A secondary-side controller is configured to control the active clamp FET across a galvanic isolation barrier.

Abstract: Systems, methods, and apparatus receive a corrupted packet of an original packet and at least one corrupted retransmitted packet of the original packet and generate a decision packet for the original packet based on identical bits of the original packet received through the corrupted packet and the at least one corrupted retransmitted packet. Embodiments verify the decision packet to determine whether the decision packet is correct based on a last one of the at least one corrupted retransmitted packet and a one or more cyclic redundancy check (CRC) operations.