Abstract: Systems, methods, and devices that enable coexistence of traffic for collocated transceivers are described herein. In an example embodiment, a method may comprise: receiving a QuietIE request from a wireless device communicatively coupled to a first transceiver; generating, using a processing device, a QuietIE schedule for the first transceiver and the wireless device based on a transmission parameter identifying one or more transmission times designated by a transmission protocol of a second transceiver, where the second transceiver is collocated with the first transceiver and shares a transmission medium with the first transceiver, and where the QuietIE schedule identifies a plurality of quiet periods and a plurality of available periods to the wireless device; and transmitting the QuietIE schedule to the wireless device.

Abstract: In a reliable multi-cast, a concealment scheme may be applied to recover or conceal lost or otherwise corrupted packets of audio information for one channel based on the audio information of other channels, in the reliable multi-cast. The concealment scheme may employ correction factors for channels derived from the channel relationships.

Abstract: An on-vehicle system comprises a Clock Extension Peripheral Interface (CXPI) bus and a device coupled to the CXPI bus as a slave node. The device comprises a transceiver configured to: generate a first signal by delaying an inverted signal of a transmission data signal; generate a second signal based on the transmission data signal, where the second signal has a low slew rate; selectively output the first signal or the second signal as a third signal, in response to a selector signal; and generate a clock signal in response to the third signal, where the clock signal is at a high level when the third signal is at a low level, and where the clock signal is at the low level when the third signal is at the high level.

Abstract: A nonvolatile memory device can include a serial port having at least one serial clock input, and at least one serial data input/output (I/O) configured to receive command, address and write data in synchronism with the at least one serial clock input. At least one parallel port can include a plurality of command address inputs configured to receive command and address data in groups of parallel bits and a plurality of unidirectional data outputs configured to output read data in parallel on rising and falling edges of a data clock signal. Each of a plurality of banks can include nonvolatile memory cells and be configurable for access by the serial port or the parallel port. When a bank is configured for access by the serial port, the bank is not accessible by the at least one parallel port. Related methods and systems are also disclosed.

Abstract: In an example embodiment, a device comprises one or more processors and a baseband controller. The one or more processors are configured to: determine, from a payload of at least one received packet, a channel identification (ID) of a notice window in a sequence of transmission windows; transmit, in the notice window, a notice packet that identifies a target window, the target window being later in the sequence of transmission windows than the notice window; generate a target packet that includes inverse whitened data; and transmit the target packet in the target window. The baseband controller is configured to execute signal whitening on the target packet, where the signal whitening of the inverse whitened data in the target packet results in a substantially sinusoidal signal when the target packet is transmitted by the device.

Abstract: A system and method for determining position information. The method includes selecting a column, a first row, and a second row of a capacitive sensor array. The first row and second row intersect with the column of the capacitive sensor array. The method further includes measuring a differential capacitance between the first row and the second row and utilizing the differential capacitance in determining a location of an object proximate to the capacitive sensor array.

Abstract: Systems, methods, and devices enable coexistence of traffic for collocated transceivers. Methods may include generating, using a processing device, a target-wake-time (TWT) agreement, the TWT agreement being determined based on availability of a first transceiver and a plurality of wireless devices. The methods may also include generating, using the processing device, a medium access schedule for the first transceiver based on a transmission parameter of a second transceiver, the second transceiver being collocated with the first transceiver and sharing a transmission medium with the first transceiver, and the medium access schedule being a TWT schedule. The methods may further include transmitting the TWT schedule to the plurality of wireless devices, the TWT schedule identifying a plurality of wake times and a plurality of sleep times to the plurality of wireless devices.

Abstract: A method is disclosed to estimate energy consumed by a component in a microcontroller during operation including identifying “event” activities, where the energy consumed by the component may be determined by the number of events executed by the component, and “duration” activities, where the energy consumed may be determined by the duration of time required to execute of the activity, and determining the energy consumed by the component based on the number of events/duration of time and an energy coefficient which corresponds to the amount of energy consumed by the component to execute the activity, under given operating conditions. In an embodiment, data transfers at a bus interface may represent event activities. Apparatus to estimate the energy consumed is disclosed including bus monitors to receive signals representing data transfers at a bus interface and provide signals indicating the number of data transfers executed.

Abstract: A semiconductor device that has a silicon-oxide-nitride-oxide-silicon (SONOS) based non-volatile memory (NVM) array including charge-trapping memory cells arranged in rows and columns and configured to store one of N×analog values. Each charge-trapping memory cells may include a memory transistor including an angled lightly doped drain (LDD) implant extends at least partly under an oxide-nitride-oxide (ONO) layer of the memory transistor. The ONO layer disposed within the memory transistor and over an adjacent isolation structure has the same elevation substantially.

Abstract: A semiconductor device that has a semiconductor-oxide-nitride-oxide-semiconductor (SONOS) based non-volatile memory (NVM) array including NVM cells arranged in rows and columns, in which NVM transistors of the NVM cells are configured to store N×analog values corresponding to the N×levels of their drain current (ID) or threshold voltage (VT) levels, digital-to-analog (DAC) function that receives and converts digital signals from external devices, column multiplexor (mux) function that is configured to select and combine the analog value read from the NVM cells, and analog-to-digital (ADC) function that is configured to convert analog results of the column mux function to digital values and output the digital values.

Abstract: A semiconductor device that has a semiconductor-oxide-nitride-oxide-semiconductor (SONOS) based non-volatile memory (NVM) array including NVM cells arranged in rows and columns, in which NVM transistors of the NVM cells are configured to store N×analog values corresponding to the N×levels of their drain current (ID) or threshold voltage (VT) levels, digital-to-analog (DAC) function that receives and converts digital signals from external devices, column multiplexor (mux) function that is configured to select and combine the analog value read from the NVM cells, and analog-to-digital (ADC) function that is configured to convert analog results of the column mux function to digital values and output the digital values.

Abstract: A secondary controlled AC-DC converter including an oscillator in a primary-side controller (PSC), and method for operating the same to enable soft-start and low frequency operation are provided. Generally, the method includes driving a power switch coupled between an AC input and a primary-side of the converter with a gate-drive (GD-signal). At startup and following auto-restart the GD-signal is generated using an oscillator-signal from the oscillator. After receiving start-stop pulses from a secondary-side controller, the oscillator-signal is decoupled from the GD-signal using a controller in the PSC, and the PSC begins generating the GD-signal using pulse-width-modulated (PWM) generated using the start-stop pulses. The oscillator operates at a first frequency independent of the PWM signal. The PWM signal includes one of a number of frequencies selected based on a power drawn from the converter, and, in low power applications can be less than the first frequency.

Abstract: A semiconductor device includes a semiconductor chip, a bump contract, and encapsulating layer, an insulating layer, and a connection terminal.

Abstract: A method can include receiving a timing signal that is part of a first communication protocol; by operation of a master device operating according to a second communication protocol, determining event timing windows for a plurality of slave devices of the master device; and by operation of the master device, transmitting control packets to the slave devices, adjusting clock values in the slave devices to sequentially order the event timing windows within an event group window; wherein the event window is timed according to the timing signal. Related devices and systems are also disclosed.

Abstract: A fingerprint sensor-compatible overlay material which uses anisotropic conductive material to enable accurate imaging of a fingerprint through an overlay is disclosed. The anisotropic conductive material has increased conductivity in a direction orthogonal to the fingerprint sensor, increasing the capacitive coupling of the fingerprint to the sensor surface, allowing the fingerprint sensor to accurately image the fingerprint through the overlay. Methods for forming a fingerprint sensor-compatible overlay are also disclosed.

Abstract: A peripheral device includes a function block to provide data in response to a request from a host device, a data channel coupled with the function block to transmit the data from the function block to a host device as one or more packets, and output logic coupled with the data channel and configured to indicate validity of the data transmitted via the data channel by causing a signal to transition for each of the one or more packets of the data transmitted to the host device via the data channel, and transmit the signal to the host device.

Abstract: Systems and methods of forming such include method, forming a memory gate (MG) stack in a first region, forming a sacrificial polysilicon gate on a high-k dielectric in a second region, wherein the first and second regions are disposed in a single substrate. Then a select gate (SG) may be formed adjacent to the MG stack in the first region of the semiconductor substrate. The sacrificial polysilicon gate may be replaced with a metal gate to form a logic field effect transistor (FET) in the second region. The surfaces of the substrate in the first region and the second region are substantially co-planar.

Abstract: A device includes a reservation pattern detector to detect a pattern of medium reservations in which a sum of reservation durations associated with two or more frames received from a first wireless device meets or exceeds a threshold duration value, and a reservation mitigator coupled with the reservation pattern detector to, responsive to detecting the pattern of medium reservations, provide a mitigation operation to prevent a second wireless device from yielding the medium to the first wireless device.

Abstract: A design system is provided. In one embodiment the design system includes an input module to receive specification data for a designed circuit including a configurable integrated circuit (IC). The configurable IC includes a number of analog elements for which parameters can be set by the design system, and a plurality of configurable signal path elements including an analog-to-digital converter (ADC) that is utilized in a plurality of different signal paths. The design system further includes a design module to generate a design for the designed circuit based on the specification data, and an output module to set parameters of at least one of the analog elements based on the design. Other embodiments are also provided.

Abstract: Disclosed are systems and methods for diagnosing the health of a plurality of memory cells in a memory array. Diagnostics are initiated from a remote server via an encrypted channel on the memory device embedded in an end-use system. The memory device includes a plurality of memory cells in a memory array. At the remote server, encrypted diagnostics data is received in response to execution of a diagnostics program by the memory device on the plurality of memory cells. The diagnostics data pertains to the health of the memory cells. The encrypted diagnostics data is decrypted into decrypted diagnostics data and the decrypted diagnostics data is analyzed to determine the health of the memory cells. Failure mitigation is performed for the memory device if the analyzing indicates unhealthy memory cells.