Abstract: Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, a method for suppression of program disturb in a flash memory array is provided. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). During a program memory operation, a first voltage, of a selected SG line, and a second voltage, of an unselected BL, are regulated independently of a power supply voltage of the flash memory array, where the first voltage is regulated in a first range of 0.9V to 1.1V and the second voltage is regulated in a second range of 0.4V to 1.2V.

Abstract: Example apparatus, systems, and methods receive, by a current digital-to-analog converter (DAC) of a shunt regulator, a first digital code indicative of a first programmable power supply command specifying a first programmable output voltage (Vbus) to be delivered to a voltage bus of a USB-compatible device. The programmable power supply command is compatible with a universal serial bus—power delivery (USB-PD) standard. Responsive to receipt of the first digital code, adjust, by the current DAC, a sink current delivered to a feedback node to adjust an output voltage to the first Vbus for dynamic programmability. The feedback node is coupled to a first input of an amplifier of the shunt regulator and the first Vbus is programmable.

Abstract: A microcontroller comprises a plurality of digital peripheral blocks and a direct memory access (DMA) controller coupled thereto. The plurality of digital peripheral blocks includes a digital peripheral block that is configured to issue a DMA request. Upon receipt of the DMA request, the DMA controller is configured to retrieve configuration information and to write the configuration information to a configuration register associated with a circuit element of the microcontroller.

Abstract: Systems and/or methods are provided that facilitate employing a variable read latency on a serial memory bus. In an aspect, a memory can utilize an undefined amount of time to obtain data from a memory array and prepare the data for transfer on the serial memory bus. The serial memory bus can be driven to a defined state. When data is ready for transfer, the memory can assert a start bit on the serial memory bus to notify a host prior to initiating the data transfer.

Abstract: A differential-slope-limiting-switch and method are provided. Generally, the switch includes a first transistor having a first source-drain (SD) and well coupled to a first port of the switch, a gate, and a second SD, and a second transistor having a first SD and well coupled to a second port, a gate, and a second SD coupled to the second SD of the first transistor. A selector-circuit couples the gate of the first transistor to a first current-source when a signal to close the switch is received, and to the first port when it is not received. A second selector-circuit couples the gate of the second transistor to a second current-source when the signal is received, or to the second port. First and second feedback-capacitors couple each gate to the port on opposite sides of the switch and with the current-sources limit a slope of voltage transitions across the closed switch.

Abstract: Example apparatus, systems and methods receive a new firmware image at a memory device and place the new firmware image into second nonvolatile storage locations of the memory device such that the second nonvolatile storage locations do not overlap with first nonvolatile storage locations of the memory device that store a current firmware image. Embodiments place a logical address to physical address mapping for the new firmware image into a remap data structure stored in memory circuits of the memory device. The remap data structure also includes a logical address to physical address mapping for the current firmware image. Embodiments provide a first status value to indicate that the logical address to physical address mapping for the new firmware image is a valid firmware image and a second status value to indicate that the logical address to physical address mapping for the current firmware image is an invalid firmware image.

Abstract: A system includes a transmitter configured to transmit an original packet. The system also includes a receiver comprising a processing device. The processing device is configured to receive a corrupted Bluetooth® packet of the original packet and at least one retransmitted packet of the original packet. The processing device is also configured to generate an accumulated packet based on the corrupted packet and the at least one retransmitted packet, and generate a decision packet for the original packet based on the accumulated packet. The processing device is further configured to verify the decision packet to determine whether the decision packet is correct.

Abstract: Disclosed are methods and systems for a WLAN device to select an operating dynamic frequency selection (DFS) channel that minimizes the probability of radar interference by using aiding information. The aiding information may be a crowd-sourced database of geo-tagged radar zones including one or more DFS channels used within the geo-tagged radar zones that are detected by a plurality of WLAN devices. The WLAN device may query the crowd-sourced database for a geo-tagged radar zone that is nearby to determine if a radar operates on an overlapping DFS channel so it may switch to a different channel. In one aspect, the aiding information may be periodic special action frames broadcast by a WLAN beaconing device over the operating channel of the WLAN device. The special action frames may carry information on one or more channels used by a near-by radar and recommended alternative channels to use by the WLAN device.

Abstract: A method includes using a memory address map, locating a first portion of an application in a first memory and loading a second portion of the application from a second memory. The method includes executing in place from the first memory the first portion of the application, during a first period, and by completion of the loading of the second portion of the application from the second memory. The method further includes executing the second portion of the application during a second period, wherein the first period precedes the second period.

Abstract: A method, apparatus, and system measure, at a first channel of a processing device, a first signal indicative of a touch object proximate to an electrode layer. The first signal includes a touch data component and a first noise component generated by a noise source. The method, apparatus, and system measure, at a second channel of the processing device, a second signal including a second noise component generated by the noise source. The second channel is coupled to a shield layer disposed between the noise source and the electrode layer. The method, apparatus, and system generate an estimated noise signal using the second noise component of the second signal that is associated with the second channel. The method, apparatus, and system subtract the estimated noise signal from the measured first signal to obtain the touch data component of the first signal.

Abstract: A method includes receiving at a wireless access point a first probe request from a first client device requesting connection with the wireless access point via a first frequency band, queueing the first client device in response to an indication that the first client device supports connection via the second frequency band, and in response to receiving at the wireless access point a second probe request from the first client device requesting connection with the wireless access point via the second frequency band, establishing a connection between the wireless access point and the first client device using the second frequency band.

Abstract: Systems, methods, and apparatus receive a signal from a first wireless device through a first antenna, of a plurality of antennas, the signal including a first segment and a second segment. Responsive to detecting a change in the signal from the first segment to the second segment, embodiments traverse the plurality of antennas to receive the second segment through each of the plurality of antennas. Embodiments determine a plurality of phase samples, each associated with the second segment received through one of the plurality of antennas. Embodiment then use the plurality of phase samples to calculate direction data associated with the first wireless device.

Abstract: A semiconductor device that has a split gate charge trapping memory cell having select and memory gates of different heights is presented herein. In an embodiment, the semiconductor device also has a low voltage transistor and a high voltage transistor. In one embodiment, the gates of the transistors are the same height as the select gate. In another embodiment, the gates of the transistors are the same height as the memory gate.

Abstract: Disclosed are apparatus and methods for programming a plurality of nonvolatile memory (NVM) devices. Each NVM device self-generates and stores a unique encryption key. Each NVM device concurrently receives an image from a multiple-device programming system to which all the NVM devices are communicatively coupled. Each NVM device encrypts the received image using such NVM device's unique encryption key to produce a unique encrypted image for each NVM device. Each NVM device stores its unique encrypted image within a nonvolatile memory of such NVM device. The unique encryption key can then be securely transferred to a host device for decrypting the image accessed from one of the NVM devices.

Abstract: One embodiment includes and I/O bus including a signal line coupled to a signal source and multiple line switches, each line switch to couple a corresponding I/O port to the signal line. Switch logic coupled to the I/O bus may programmatically switch the multiple line switches to couple at least one of the signal source and measurement circuitry to the respective I/O port.

Abstract: A circuit, system, and method for measuring or detecting pressure or force of a fingerprint on an array of electrodes is described. Pressure or force may be measured or detected using a processed image of the fingerprint, or by measurement of capacitance of deformed variable capacitors.

Abstract: A programmable device, having an analog component coupled with an analog bus and a digital component coupled with a digital bus together with a set of 10 pads, each of which capable of being coupled to a bus line of one segment of the analog bus as well as to at least one digital bus line, and where the analog bus is capable of being used to connect a pair of the pads to each other.

Abstract: Controlling gate-source voltage with a gate driver in a secondary-side controller in a secondary-controlled converter is described. In one embodiment, an apparatus includes a provider field effect transistor (FET) coupled to a transformer and the secondary-side controller coupled to the transformer. The gate driver is integrated on the secondary-side controller and is configured to control the gate-source voltage and slew rate of the secondary-side FET.

Abstract: A memory string is disclosed including a plurality of core cells serially connected between a source select gate and a drain select gate along a channel. Each core cell includes a wordline separated from the channel by a stack of layers including a charge trapping layer. At least one of the source and drain select gates is a stacked select gate with a plurality of components, including a first component adjacent to the plurality of core cells and a second component separated from the core cells by the first component. The first component includes a wordline separated from the channel by a stack of layers including a charge trapping layer, and a distance between the wordline of the first component and the wordline of a first core cell in the plurality of core cells is substantially the same as distances between each wordline in the plurality of word core cells.

Abstract: A system includes an apparatus and a station. The apparatus includes a first access point (AP) function configured to operate on a first channel of a first frequency band and a second AP function configured to operate on a second channel of a second frequency band. The apparatus also includes a processing device. In response to detecting that the second channel is unavailable for use by the second AP function, the processing device is configured to transition the second AP function to operate on a third channel of the first frequency band. The station can be used in an automotive application and is configured to communicate with the first AP function in the first frequency band, or communicate with the second AP function in the first frequency band or the second frequency band.