Abstract: In an example embodiment, a communication system provides a clock extension peripheral interface (CXPI) communication bus that is coupled to a master node and a plurality of slave nodes. The master node is configured to transmit a reference clock signal on the CXPI communication bus. Each slave node of the plurality of slave nodes is configured to receive the reference clock signal from the CXPI communication bus and to transmit and receive data to and from the CXPI communication bus based on the reference clock signal.

Abstract: A device and method that includes a shunt regulator of a universal serial bus (USB) compatible power supply device is disclosed. The shunt regulator includes an amplifier with an output, a first input, and a second input. The shunt regulator also includes a current digital-to-analog converter (DAC) that is coupled to the first input of the amplifier and a voltage bus node. The current DAC adjusts a sink or a source current delivered at the first input of the amplifier to regulate a programmable output voltage (Vbus) in the USB-compatible power supply device. The current delivered by the DAC is responsive to receipt of a digital code indicative of a programmable power supply command specifying the Vbus to be delivered by the USB-compatible power supply device on the voltage bus node.

Abstract: A method, apparatus, and system measure, at a first channel of a processing device, a first signal indicative of a touch object proximate to an electrode layer. The first signal includes a touch data component and a first noise component generated by a noise source. The method, apparatus, and system measure, at a second channel of the processing device, a second signal including a second noise component generated by the noise source. The second channel is coupled to a shield layer disposed between the noise source and the electrode layer. The method, apparatus, and system generate an estimated noise signal using the second noise component of the second signal that is associated with the second channel. The method, apparatus, and system subtract the estimated noise signal from the measured first signal to obtain the touch data component of the first signal.

Abstract: A structure and method for providing improved and reliable charge trapping memory device are disclosed herein. A charge trapping field effect transistor (FET) comprising a semiconductor substrate, a doped region in the semiconductor substrate, and a gate structure on the semiconductor substrate and a method of fabricating the same are also discussed. The doped region comprises a first lateral dimension along a first direction. The gate structure comprises a charge trapping dielectric region and a charge trapping conductive region in contact with the charge trapping dielectric region.

Abstract: An apparatus including non-volatile memory to store a forensic key and data, the data received from a host computing system. A processing device is coupled to the non-volatile memory and is to: allow writing the data, by the host computing system, to a region of the non-volatile memory; in response to a lock signal received from the host computing system, assert a lock on the region of the non-volatile memory, the lock to cause a restriction on access to the region of the non-volatile memory by an external device; and provide unrestricted access, by the external device, to the region of the non-volatile memory in response to verification of the forensic key received from the external device.

Abstract: A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manger coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a lower power mode.

Abstract: An apparatus for inductive sensing or capacitive sensing is described. The apparatus may include a signal generator to output on a first terminal a first signal in a first mode and a second signal in a second mode. The apparatus may include a charge measuring circuit to receive on a second terminal a third signal in the first mode and a fourth signal in the second mode. The third signal is representative of an inductance of a sense unit coupled between the first terminal and the second terminal. The fourth signal is representative of a capacitance of the sense unit.

Abstract: An example secure embedded device includes a secure non-volatile memory coupled to a processor. The processor provides a scramble or cipher key and uses a scramble algorithm or a cipher algorithm to scramble or cipher information received from an external device into transformed information. The processor writes a least a portion of the transformed information to a plurality of memory locations of the secure non-volatile memory. The plurality of memory locations is based on the scramble or cipher key.

Abstract: An electronic device includes a first electronic circuitry portion configured to connect a VCONN supply terminal of a Universal Serial Bus Type-C (USB-C) controller to a first configuration channel (CC) terminal of a plurality of CC terminals of the USB-C controller. The first CC terminal of the USB-C controller is to be directly connected to a first CC terminal of a plurality of CC terminals of a USB-C receptacle. The electronic device further includes a second electronic circuitry portion electrically coupled to the first electronic circuitry portion and configured to detect a voltage across the first CC terminal of the USB-C controller and the VCONN supply terminal. The second electronic circuitry portion is to decouple the VCONN supply terminal from the first CC terminal of the USB-C controller when the voltage is greater than a predetermined threshold.

Abstract: Devices and methods for forming charge storage regions are disclosed. In one embodiment, a semiconductor device comprises a semiconductor layer having a trench, charge storage layers formed at both side surfaces of the trench, a wordline buried in the trench in contact with the charge storage layers, and source-drain regions formed in the semiconductor layer at both sides of the trench.

Abstract: Systems, methods, and devices enable the implementation of antenna diversity techniques. Devices include a first wireless communications device that includes a plurality of antennas, and a transceiver coupled to the plurality of antennas and configured to send and receive data in accordance with a wireless transmission protocol, while the peer wireless communication device may have a single antenna or multiple antennas. Devices also include a processor configured to, in a first mode, calculate an angle of arrival (AoA) with the plurality of antennas or an angle of departure (AoD) associated with single antenna, and, in a second mode, send data to and receive data from a second wireless communications device via at least a first antenna of the plurality of antennas, where the first antenna is selected by the processor based on one of a first plurality of signal measurements between the first and second wireless communications devices.

Abstract: A method can include receiving a timing signal that is part of a first communication protocol; by operation of a master device operating according to a second communication protocol, determining event timing windows for a plurality of slave devices of the master device; and by operation of the master device, transmitting control packets to the slave devices, adjusting clock values in the slave devices to sequentially order the event timing windows within an event group window; wherein the event window is timed according to the timing signal. Related devices and systems are also disclosed.

Abstract: A method can include, by operation of first communication circuits, determining a quality of a plurality of communication frequencies according to wireless communications of a first protocol type; recording a quality of the communication frequencies; selecting communication frequencies for use by second communication circuits based on the quality of the communication frequencies; and wirelessly transmitting and receiving data with the second communication circuits according to a second protocol different than the first protocol; wherein the first and second communication circuits are collocated on the same device. Related devices and systems are also disclosed.

Abstract: A method can include receiving frequency hop configuration data for a first wireless communication protocol via a second wireless communication protocol in second communication circuits; and configuring first communication circuits to communicate according to the first communication protocol with frequency hopping indicated by the frequency hop configuration data; wherein the first communication circuits and second communication circuits are formed in a same combination device. Related devices and systems are also disclosed.

Abstract: A method can include monitoring a transmission medium for packets of a first protocol type with first communication circuits while the medium is controlled by second communication circuits. Requesting access to the medium in response to the first communication circuits detecting a packet of the first protocol type. Upon being granted access to the medium, executing a data transmission operation. Yielding the medium back to the second communication circuits in response the first communication circuits completing the data transmission operation. Related devices and systems are also disclosed.

Abstract: Example systems and methods of a wireless device use first communication circuitry of the wireless device to determine a first signal level associated with a first radio frequency signal and use second communication circuitry of the wireless device to determine a second signal level associated with a second radio frequency signal. Systems and methods generate a sensitivity adjustment value based on the first signal level and the second signal level, and use the sensitivity adjustment value to process a combined signal comprising the first radio frequency signal and the second radio frequency signal.

Abstract: Systems and/or methods are provided that facilitate employing a variable read latency on a serial memory bus. In an aspect, a memory can utilize an undefined amount of time to obtain data from a memory array and prepare the data for transfer on the serial memory bus. The serial memory bus can be driven to a defined state. When data is ready for transfer, the memory can assert a start bit on the serial memory bus to notify a host prior to initiating the data transfer.

Abstract: Implementations disclosed describe techniques to optimize performance of wireless networks having multi-band connectivity by steering devices connecting to the network to preferred frequency ranges. In an example embodiment, a method may comprise receiving, a first probe request from a client device at a first access point of the wireless network, establishing a first association between the first access point and the client device, the first access point operating at a first frequency range of the wireless network, receiving a second probe request from the client device at a second access point, the second access point operating at a second frequency range of the wireless network, sending a transition request over the first access point to instruct the client device to transition to the second access point, and establishing a second association between the second access point and the client device.

Abstract: A method includes using a direct memory access controller, transferring first data from a memory to an input/output control circuit via a first bus and transferring the first data from the input/output control circuit to an authentication processing circuit via a second bus, without using the first bus. The method includes using the authentication processing circuit, generating authentication data based on the first data and transferring the first data from the input/output control circuit to a cryptography processing circuit via a third bus, without using the first bus. Responsive to authentication of the first data by a first CPU coupled to the first bus, the method includes using the cryptography processing circuit, decrypting the first data, and using the direct memory access controller, transferring the decrypted first data from the input/output control circuit to the memory via the first bus.

Abstract: Systems, methods, and devices that enable coexistence of traffic for collocated transceivers are described herein. In an example embodiment, a method may comprise: receiving a QuietIE request from a wireless device communicatively coupled to a first transceiver; generating, using a processing device, a QuietIE schedule for the first transceiver and the wireless device based on a transmission parameter identifying one or more transmission times designated by a transmission protocol of a second transceiver, where the second transceiver is collocated with the first transceiver and shares a transmission medium with the first transceiver, and where the QuietIE schedule identifies a plurality of quiet periods and a plurality of available periods to the wireless device; and transmitting the QuietIE schedule to the wireless device.