Patents Assigned to Cypress Semiconductor
  • Accurate feed-forward sensing in flyback-transformer based secondary controller
    Patent number: 10693384
    Abstract: A secondary side controller for an AC-DC converter and method for operating the same are provided. Generally, the controller includes a single synchronous rectifier sense (SR-SNS) pin coupled to a drain of a SR on a secondary of a transformer to sense a voltage (VSRD). In feed-forward (FF) mode VSRD is a sum of a voltage (VIN) on a primary divided by a turn-ratio (N) of the transformer and an output bus voltage (VBUS). A voltage-to-current (V2I) converter coupled to the SR-SNS pin and to the output bus removes VBUS from VSRD. A sample and hold (S/H) module coupled to the SR-SNS pin samples a voltage (VSAMP) including information on VIN/N. A VIN/N V2I converter coupled to the S/H module converts VSAMP to a feed-forward current (IFF), and a cancellation and signal module coupled thereto extracts information on VIN from IFF and generates signals to control the AC-DC converter.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: June 23, 2020
    Assignee: Cypress Semiconductor Corporation
    Inventors: Partha Mondal, Hemant P. Vispute, Arun Khamesra, Hariom Rai, Pulkit Shah
  • SYSTEMS, METHODS, AND DEVICES FOR USER CONFIGURABLE WEAR LEVELING OF NON-VOLATILE MEMORY
    Publication number: 20200192583
    Abstract: In an example embodiment, a device comprises a non-volatile memory and wear leveling control circuitry. The non-volatile memory comprises logical memory sectors mapped to physical memory sectors, and a supervisory memory sector configured to store a mapping of the logical memory sectors to memory partitions with user-defined boundaries. The wear leveling control circuitry is configured to: receive and store, in the mapping, wear leveling parameters based on user input, where each memory partition is associated with a wear leveling parameter indicating whether that memory partition is excluded from wear leveling; and determine and apply, to the non-volatile memory, wear leveling characteristics based on the wear leveling parameters, where the wear leveling characteristics identify an amount of wear leveling allowed for each of the memory partitions.
    Type: Application
    Filed: October 16, 2019
    Publication date: June 18, 2020
    Applicant: Cypress Semiconductor Corporation
    Inventors: Mark Alan McClain, Willy Obereiner, Rainer Hoehler
  • Multi-layer inter-gate dielectric structure and method of manufacturing thereof
    Patent number: 10686044
    Abstract: A memory device that has a first gate disposed adjacent to a second gate and a first dielectric structure disposed between the first and second gates. The first dielectric structure has at least four layers of oxide and nitride films arranged in an alternating layer, in which each of the at least four or more layers includes a width in an approximate range of 30 ? or less. The first dielectric structure further includes a top surface that is substantially un-etched.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: June 16, 2020
    Assignee: Cypress Semiconductor Corporation
    Inventors: Chun Chen, Shenqing Fang
  • Suppression of program disturb with bit line and select gate voltage regulation
    Patent number: 10685724
    Abstract: Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, a method for suppression of program disturb in a flash memory array is provided. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). During a program memory operation, a first voltage, of a selected SG line, and a second voltage, of an unselected BL, are regulated independently of a power supply voltage of the flash memory array, where the first voltage is regulated in a first range of 0.9V to 1.1V and the second voltage is regulated in a second range of 0.4V to 1.2V.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: June 16, 2020
    Assignee: Cypress Semiconductor Corporation
    Inventors: Chun Chen, Kuo Tung Chang, Yoram Betser, Shivananda Shetty, Giovanni Mazzeo, Tio Wei Neo, Pawan Singh
  • Auto-switching communication interface
    Patent number: 10684974
    Abstract: A touch detection system in accordance with one embodiment of the invention can include a circuit for converting a capacitance to a digital value. The touch detection system can include first and second communication interface circuits for enabling a first and second communication protocols, respectively. Furthermore, the touch detection system can include a detector circuit coupled to the first communication interface circuit and the second communication interface circuit. The detector circuit can be for automatically detecting a factor that indicates automatically enabling the first communication interface circuit and automatically disabling the second communication interface circuit. The detector circuit can be for detecting a coupling of a pin of the first communication interface circuit that is not used by the second communication interface circuit.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: June 16, 2020
    Assignee: Cypress Semiconductor Corporation
    Inventor: David G. Wright
  • ENERGY-EFFICIENT IDLE LISTENING SCHEMES
    Publication number: 20200187114
    Abstract: Two methods for energy-efficient idle listening enhancement for WLAN systems are provided. The first method performs a change of operation of a station (STA) from an active mode to an idle listening mode without notifying the change to an access point (AP) associated with the STA. In the idle listening mode, the AP may transmit frames to the STA using a higher bandwidth, but the STA can only sense channels in a lower bandwidth to save energy. The second method transmits a frame to the AP associated with the STA to notify the AP the change of operation of the STA from the active mode to the idle listening mode. In the idle listening mode, the AP may transmit frames to the STA using the lower bandwidth, and the STA can only sense channels in the lower bandwidth to save energy.
    Type: Application
    Filed: October 2, 2019
    Publication date: June 11, 2020
    Applicant: Cypress Semiconductor Corporation
    Inventors: Kamesh Medapalli, Rajendra Kumar Gundu Rao, Xianmin Wang, Sangho Seo
  • Devices, systems and methods for connecting and authenticating local devices to common gateway device
    Patent number: 10681544
    Abstract: A method can include detecting local devices with a wireless first communication interface (IF) of a gateway device; authenticating at least one local device with the gateway device, including by operation of the first communication IF and a second communication IF, relaying secure communications between the at least one local device and a server to enable authentication of the at least one local device by the server, and after receiving authentication of the at least one local device at the gateway device, transmitting user information for storage in a secure memory of the authenticated local device; and operating the gateway device as a common access point to the network for any of a plurality of local devices authenticated with the gateway device. Related systems and gateway devices are also disclosed.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: June 9, 2020
    Assignee: Cypress Semiconductor Corporation
    Inventors: Hui Luo, Hongwei Kong, Kaiping Li, Sungeun Lee, Sridhar Prakasam
  • Non-volatile memory device and method of blank check
    Patent number: 10679712
    Abstract: A non-volatile memory device and methods for operating the same are provided. The memory device may have multiple complementary memory cells. The method of blank check includes detecting a state value of each of the true and complementary transistors, generating an upper state value, Wherein a first predetermined amount of the true and complementary transistors have greater state values than the upper state value, generating a lower state value, wherein a second predetermined amount of the true and complementary transistors have less state values than the lower state value, generating a state value range based on a difference between the upper state value and the lower state value, and comparing the state value range to a threshold value to determine whether the plurality of complementary memory cells is in a blank state or a non-blank state. Other embodiments are also disclosed herein.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: June 9, 2020
    Assignee: Cypress Semiconductor Corporation
    Inventors: James Pak, Shivananda Shetty, Yoram Betser, Amichai Givant, Jonas Neo, Pawan Singh, Stefano Amato, Cindy Sun, Amir Rochman
  • POWER SUPPLY ARCHITECTURE FOR USB-C CONTROLLERS
    Publication number: 20200174546
    Abstract: In an example embodiment, a Universal Serial Bus Type-C (USB-C) cable comprises a respective integrated circuit (IC) controller, disposed at each end of cable, that is coupled to a respective VCONN line at that end of the cable. Each IC controller comprises a power rail, a VDDD terminal, a VBUS terminal, and a VCONN terminal that is coupled to the VCONN line at the respective end of the cable. The VDDD terminal, the VCONN terminal, and the VBUS terminal are coupled to the power rail. The power rail is coupled to internal circuits of the IC controller and is configured to provide operating power to the internal circuits of the IC controller from the its VCONN terminal.
    Type: Application
    Filed: November 21, 2019
    Publication date: June 4, 2020
    Applicant: Cypress Semiconductor Corporation
    Inventors: Nicholas Alexander Bodnaruk, Anup Nayak, Pavan Kumar Kuchipudi
  • DYNAMIC ANTENNA ARRAY PATTERN SWITCHING IN WIRELESS SYSTEMS
    Publication number: 20200178054
    Abstract: An example method of operating a device includes using a switching circuitry to a first subset of antennas from an antenna cluster, using the first subset of antennas to receive a first Bluetooth signal, generating a first directional value of the first Bluetooth signal, using a processing element to evaluate at least one antenna of the antenna cluster based at least partly on the first directional value, selecting a second subset of antennas based on evaluation, using the second subset of antennas to receive a second Bluetooth signal, and generating a second directional value of the second Bluetooth signal. Other embodiments of the device and operations thereof are also disclosed.
    Type: Application
    Filed: March 6, 2019
    Publication date: June 4, 2020
    Applicant: Cypress Semiconductor Corporation
    Inventor: Victor Simileysky
  • NAND MEMORY CELL STRING HAVING A STACKED SELECT GATE STRUCTURE AND PROCESS FOR FOR FORMING SAME
    Publication number: 20200168618
    Abstract: A memory string is disclosed including a plurality of core cells serially connected between a source select gate and a drain select gate along a channel. Each core cell includes a wordline separated from the channel by a stack of layers including a charge trapping layer. At least one of the source and drain select gates is a stacked select gate with a plurality of components, including a first component adjacent to the plurality of core cells and a second component separated from the core cells by the first component. The first component includes a wordline separated from the channel by a stack of layers including a charge trapping layer, and a distance between the wordline of the first component and the wordline of a first core cell in the plurality of core cells is substantially the same as distances between each wordline in the plurality of word core cells.
    Type: Application
    Filed: January 20, 2020
    Publication date: May 28, 2020
    Applicant: Cypress Semiconductor Corporation
    Inventors: Ming Sang Kwan, Shenqing Fang, Youseok Suh, Michael A. VAN BUSKIRK
  • SYSTEM LEVEL INTERCONNECT WITH PROGRAMMABLE SWITCHING
    Publication number: 20200169259
    Abstract: A method for operating a system level interconnect in an integrated circuit (IC) is provided in an example embodiment. The method comprises: writing, by a microcontroller in the IC, a first configuration value into a configuration register, where the first configuration value programs the system level interconnect to couple a first peripheral to a second peripheral; monitoring the IC to determine an operational state of the IC; and in response to determining a change in the operational state of the IC, writing by the microcontroller a second configuration value into the configuration register to dynamically change interconnections in the system level interconnect between the first peripheral and the second peripheral.
    Type: Application
    Filed: November 19, 2019
    Publication date: May 28, 2020
    Applicant: Cypress Semiconductor Corporation
    Inventors: Bert Sullam, Warren Snyder, Haneef Mohammed
  • Programmable input/output circuit
    Patent number: 10666258
    Abstract: A programmable input/output (I/O) circuit includes an output buffer coupled between an output signal and an I/O pad and an input comparator coupled between an input signal and the I/O pad. The input comparator includes a first input coupled to the I/O pad. A multiplexor receives a select signal for selecting a first reference voltage from the plurality of reference voltages at a first time and for dynamically selecting a second reference voltage from the plurality of reference voltages at a second time.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: May 26, 2020
    Assignee: Cypress Semiconductor Corporation
    Inventors: Timothy John Williams, David G. Wright, Gregory John Verge, Bruce E. Byrkett
  • TIMESTAMP BASED ONBOARDING PROCESS FOR WIRELESS DEVICES
    Publication number: 20200162916
    Abstract: A method, apparatus, and system for provisioning a device onto a network using a non-secure communication channel between the device and a provisioner is described. The provisioner receives a timestamp-based on-time password (TOTP), and a universal resource identifier (URI) from the device and provides the TOTP and an out-of-band (OOB) UUID to a remote server over a secure communication channel identified by the URI. The device is then provisioned onto a network based on comparisons of the UUID and the TOTP.
    Type: Application
    Filed: November 15, 2019
    Publication date: May 21, 2020
    Applicant: Cypress Semiconductor Corporation
    Inventors: Dharam Kumar, Sahana D. N, Prejith Padmanabhan, Sathish Kumar Mani
  • NON-FINGER OBJECT REJECTION FOR FINGERPRINT SENSORS
    Publication number: 20200160019
    Abstract: A method for detecting a finger at a fingerprint sensor includes detecting a presence of an object at a fingerprint sensor and, in response to detecting the presence of the object, acquiring image data for the object based on signals from the fingerprint sensor. The method further includes, for each subset of one or more subsets of the image data, calculating a magnitude value for a spatial frequency of the subset, and identifying the object as a finger based on comparing the magnitude value to a threshold.
    Type: Application
    Filed: July 18, 2019
    Publication date: May 21, 2020
    Applicant: Cypress Semiconductor Corporation
    Inventors: Andriy Ryshtun, Oleksandr Rohozin, Viktor Kremin, Oleg Kapshii
  • Communicating packets in a mesh network
    Patent number: 10659941
    Abstract: An apparatus includes a Bluetooth transceiver configured to receive a packet transmitted to a Bluetooth mesh network via a radio-frequency signal. The apparatus also includes a processing device coupled to the Bluetooth transceiver. The processing device is configured to determine a strength of the radio-frequency signal. The processing device is also configured to determine a time period based on the measure of strength of the radio-frequency signal. The processing device is further configured to determine whether the Packet was received again during the time period. The processing device is further configured to transmit the Packet to the Bluetooth mesh network in response to determining that the Packet was not received again during the time period.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: May 19, 2020
    Assignee: Cypress Semiconductor Corporation
    Inventor: Robert Hulvey
  • USB SIGNAL SWITCH CIRCUITRY USING STANDARD USB HUB AND METHOD OF OPERATION THE SAME
    Publication number: 20200151129
    Abstract: A universal serial bus (USB) apparatus that has a USB hub, a first switching unit including first end coupled to a USB peripheral port of a first device, a second switching unit including a second end coupled to the USB hub and the first switching unit and a first end configured to be coupled to a first USB device, and control circuitry operable to provide control signals to the first and second switching units, in which the first control signals cause the first and second switching units to provide connectivity between the USB peripheral port of the first device and the first USB device when the first USB device is operating as a USB host and the second control signals to provide connectivity between the USB host port to the first USB device via the USB hub when the first USB device is operating as a USB peripheral.
    Type: Application
    Filed: June 24, 2019
    Publication date: May 14, 2020
    Applicant: Cypress Semiconductor Corporation
    Inventors: David G. Wright, Shopitham Ram
  • ADJUSTABLE OVER-CURRENT DETECTOR CIRCUIT FOR UNIVERSAL SERIAL BUS (USB) DEVICES
    Publication number: 20200153228
    Abstract: In an example embodiment, a universal serial bus (USB) Type-C controller comprises a current detector circuit configured to provide over-current protection on a voltage bus (VBUS) line. The current detector circuit comprises a current sense amplifier, a reference voltage generator, and a comparator coupled to the current sense amplifier and to the reference voltage generator. The current sense amplifier is configured to receive a pair of input voltages from the VBUS line and to output an indicator signal responsive to an input voltage difference between the pair of input voltages. The reference voltage generator is configured to generate a reference voltage in response to a voltage selector signal. The comparator is configured to output an interrupt signal responsive to the indicator signal exceeding the reference voltage.
    Type: Application
    Filed: June 26, 2019
    Publication date: May 14, 2020
    Applicant: Cypress Semiconductor Corporation
    Inventors: Derwin W. Mattos, Arnab Chakraborty, Ramakrishna Venigalla, Gerard Kato, Vaidyanathan Varsha
  • Accurate valley detection for secondary controlled flyback converter
    Patent number: 10651753
    Abstract: A flyback converter with secondary side control and synchronous rectifier (SR) architecture and method for operating the same are provided. Generally, the secondary side controller includes an integrated circuit (IC) including a single SR-SNS pin coupled to a drain of a SR on a secondary side of the converter to sense a voltage on the drain, and a power switch (PS) drive pin coupled to a PS on a primary side to turn on the PS in response to a number of measurements based on the voltage sensed on the drain of the SR. The IC includes a calibration block to measure a loop turn-around delay, valley delays with respect to zero-crossing and set timing for a signal to turn on the PS in response to the voltage sensed on the drain of the SR at or very close the primary side valley improving efficiency and performance of the converter.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: May 12, 2020
    Assignee: Cypress Semiconductor Corporation
    Inventors: Arun Khamesra, Hariom Rai
  • Accurate peak detection architecture for secondary controlled AC-DC converter
    Patent number: 10651754
    Abstract: An AC-DC converter with secondary side controller and synchronous rectifier (SR) architecture and method for operating the same are provided. Generally, the controller is implemented as an integrated circuit including a peak-detector module having a peak comparator with a first input coupled to a drain of the SR through a single SR sense (SR-SNS) pin to receive a sinusoidal input. A sample and hold (S/H) circuit with an input coupled to the SR-SNS pin samples the sinusoidal input and holds on an output of thereof a peak sampled voltage received on the input. A direct current (DC) offset voltage coupled between the output of the S/H circuit and the second input of the peak comparator subtracts an DC offset voltage from the peak sampled voltage to compensate for DC offset inaccuracies introduced by the S/H circuit and the peak comparator. Other embodiments are also disclosed.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: May 12, 2020
    Assignee: Cypress Semiconductor Corporation
    Inventors: Saravanan Murugesan, Karri Rajesh, Pulkit Shah, Arun Khamesra, Hariom Rai