Abstract: A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a non-volatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming.

Abstract: At least one downstream interface may be configured to be simultaneously connected to both a USB 3.0 compliant device and a USB 2.0 compliant device. The interface may be used for communicating with a USB 3.0 compliant device via a downstream port and simultaneously communicating with a USB 2.0 compliant device via the downstream port.

Abstract: A method for implementing an addressing scheme may include mapping a digital peripheral function to one or more contiguous configurable blocks in an array of configurable blocks; and assigning a memory address from a plurality of memory addresses to at least one register of each of the one or more contiguous configurable blocks based on an access mode width of the digital peripheral function and a width of each of the one or more contiguous configurable blocks.

Abstract: A capacitance sense system can include a capacitance sense input configured to receive an input signal that varies according to a sensed capacitance; an integrator/discharge circuit configured to integrate the input signal and discharge the integrated input signal toward the reference level in conversion operations; and a remainder retainer section configured to quantize the discharging of the integrated input signal, and retain any remainder of the integrated input signal that follows a quantization point for a next conversion by the integrator/discharge circuit.

Abstract: A method and apparatus for a reverse metal-insulator-metal (MIM) capacitor. The apparatus includes a lower metal layer, a bottom electrode, and an upper metal layer. The lower metal layer is disposed above a substrate layer. The bottom electrode is disposed above the lower metal layer and coupled to the lower metal layer. The upper metal layer is disposed above the bottom electrode. The upper metal layer comprises a top electrode of a metal-insulator-metal (MIM) capacitor.

Abstract: Apparatuses and methods of input attenuator circuits are described. One sensing circuit includes an attenuator circuit to receive a signal from an electrode of a sense array. The attenuator circuit is configured to attenuate input current of the signal. The attenuator circuit includes an attenuation matrix including an input terminal to receive the signal and multiple resistors. The attenuation matrix is configured to split the input current into an output current of the attenuation signal on a first output terminal and a second output current on a second output terminal. The attenuation matrix is to output the attenuated signal on the first output terminal to an integrator of the sensing circuit. The attenuator circuit also includes a buffer coupled between the attenuation matrix and the integrator. The buffer is configured to maintain a substantially same voltage at the first output terminal and the second output terminal.

Abstract: A method involves regulating an output voltage of an output transistor of a voltage regulator circuit by providing a first voltage to a front gate of the output transistor, and simultaneously with providing the first voltage to the output transistor, providing a second voltage to a back gate of the output transistor, in a manner that regulates the output voltage around a target value.

Abstract: A circuit is configured to supply a first gate voltage (PG1) at a first voltage bias (VP1) to a source of a first transistor providing an output (WLS), providing the first voltage bias (VP1) to a second transistor and supplying a second voltage bias (VN1) and a second gate voltage (NG1) to a third transistor, the second transistor coupled in series to the third transistor and in parallel with the first transistor, to supply a third voltage bias (VP2) and a third gate voltage (PG2) to a fourth transistor, and a fourth voltage bias (VN2) and a fourth gate voltage (NG2) to a fifth transistor, the fourth transistor coupled in series to the fifth transistor, and the fourth and fifth transistors coupled to a gate of the second transistor, and to provide a fifth voltage bias (VN3) to a line connecting the third transistor to the fifth transistor.

Abstract: A method and apparatus to provide random access to a programmable logic register. A processing device in a programmable logic system retrieves data from a memory of the programmable logic system. The data is loaded into a configuration register configured to store configuration data for a programmable logic function over a system bus. The processing device programs a programmable logic block to implement the programmable logic function based on the configuration data, where the processing device is configured to access a first configuration register in the configuration register set, the first configuration register corresponding to a first programmable logic block in the programmable logic system, without affecting a second configuration register corresponding to a second programmable logic block.

Abstract: A programmable system includes an input/output (I/O) pin that is configurable into multiple operational states. The programmable system further includes a memory device to store configuration data that, when provided to the I/O pin, causes the I/O pin to reconfigure into one of the operational states. When power is supplied to the system, the memory device is configured to provide the configuration data to the I/O pin prior to a system microcontroller becoming operational responsive to the power.

Abstract: A mutual capacitive sense array configured to improve edge performance in tracking user inputs is described. A mutual capacitive sense array comprises a first and second plurality of sense elements and a visual display configured below the sense array. The display is configured to contact the first plurality of sense elements, where each of the first and second plurality of sense elements has a first area and second area, respectively, and wherein the second area is less than the first area. A method is described to scan a mutual capacitive sense array for a user input, the array comprising a first, second, and third plurality of sense elements, wherein the third plurality of sense elements are arranged in parallel along the exterior edge of the mutual capacitive sense array. The third plurality of sense elements effectively reduces the tracking error occurring at the edges of the mutual capacitive sense array.

Abstract: A semiconductor device and method of fabricating the same are provided. In one embodiment, the semiconductor device includes a memory transistor with an oxide-nitride-nitride-oxide (ONNO) stack disposed above a channel region. The ONNO stack comprises a tunnel dielectric layer disposed above the channel region, a multi-layer charge-trapping region disposed above the tunnel dielectric layer, and a blocking dielectric layer disposed above the multi-layer charge-trapping region. The multi-layer charge-trapping region includes a substantially trap-free layer comprising an oxygen-rich nitride and a trap-dense layer disposed above the trap-free layer. The semiconductor device further includes a strain inducing structure including a strain inducing layer disposed proximal to the ONNO stack to increase charge retention of the multi-layer charge-trapping region. Other embodiments are also disclosed.

Abstract: An integrated circuit device may include a first integrated circuit (IC) portion having a single memory port to access at least one memory array, the single port including a first set of address, control and data paths; and a second IC portion comprising at least a first memory port and a second memory port for providing access to the memory locations of the first IC portion through the single port of the first IC portion.

Abstract: Sequencing circuitry for a ferroelectric RFID circuit includes an input node for receiving an external voltage, a bandgap circuit coupled to the input node, a bandgap ready circuit coupled to the bandgap circuit, a slew filter having an input coupled to the input node and to the bandgap ready circuit, a filter capacitor coupled to an output of the slew filter, and an LDO regulator having an input coupled to the output of the slew filter having a plurality of regulated voltages for use in a memory portion, a digital circuit portion, and for generating a reset signal. The sequencing circuitry further includes delay circuits for introducing a controlled delay between operational modes, POR cells for monitoring power supply voltages, and a digital state machine for monitoring internal nodes to control a shut-down pulse generator.

Abstract: A method for using a slider-based capacitive sensor to implement a user interface having discrete buttons. Button locations are designated on a slider-based capacitive sensor having at least two conductive traces such that a user input at any button location results in a capacitance change in the conductive traces. Locations of inputs are distinguishable by ratios between the capacitance changes of the conductive traces, which can be correlated to a particular button location. Ratio ranges corresponding to areas covered by each button are used to identify which button has received an input.

Abstract: A method includes powering multiple touch sensors using DC power derived from an AC power signal; monitoring the AC power signal and producing from the AC power signal a trigger signal that occurs repeatedly at a predetermined point in a cycle of the AC power signal; and initiating a scan of the touch sensors when the trigger signal occurs during each cycle of the AC power signal.

Abstract: Techniques for hard press rejection are described herein. In an example embodiment, a touch area on a sensor array is determined, where the touch area corresponds to a detected object and is associated with multiple signal values. A slope value for the detected object is computed based on a ratio of a signal distribution value in the touch area to a metric indicating a size of the touch area with respect to the sensor array. The slope value is compared to a threshold in order to determine whether to accept or to reject the detected object, and the detected object is rejected based on the comparison.

Abstract: The threshold voltages of particular nonvolatile memory cells on a word line are selectively increased on a column by column (cell by cell) basis. A selective program is performed on some of the cells, and simultaneously a program inhibit on other of the cells, resulting in all of the cells having a threshold voltage that falls between a minimum acceptable value and a maximum acceptable value.

Abstract: Flash memory devices and systems are provided. One flash memory device includes an n-channel metal oxide semiconductor field-effect transistor (nMOSFET), a silicon-oxide-nitride-oxide silicon (SONOS) transistor coupled to the nMOSFET, and an isolated p-well coupled to the nMOSFET and the SONOS transistor. A flash memory system includes an array of memory devices divided into a plurality of paired sectors, a global bit line (GBL) configured to provide high voltage to each respective sector during erase and program operations coupled to each of the plurality of sectors, and a plurality of sense amplifiers coupled between a respective pair of sectors. Methods for operating a flash memory are also provided. One method includes providing high voltage, via the GBL, to the paired sectors during erase and program operations and providing low voltage, via a local bit line, to each memory device during read operations.

Abstract: A SONOS memory sensing scheme includes a reference current circuit that tracks the changes in the power supply (Vcc). An equalizer of the current sense amplifier is coupled between the read out current line and the reference current line. The current sense amplifier includes data and datab (data bar) outputs which have a common mode noise due to variations in the power supply voltage. The data output is a current generated from the memory cell, and the datab output is generated by the current reference circuit.