Abstract: Systems and methods for improving the performance of dilution refrigeration systems are described. Electrostatic cryogenic cold traps employed in the helium circuit of a dilution refrigerator improve the removal efficiency of contaminants from the helium circuit. An ionization source ionizes at least a portion of a refrigerant that includes helium and number of contaminants. The ionized refrigerant passes through an electrostatic cryogenic cold trap that includes a number of surfaces at one or more temperatures along at least a portion of the fluid passage between the cold trap inlet and the cold trap outlet. A high voltage source coupled to the surfaces to causes a first plurality of surfaces to function as electrodes at a first potential and a second plurality of surfaces to function as electrodes at a second potential. As ionized contaminants release their charge on the electrodes, the contaminants bond to the electrodes.

Abstract: The systems, devices, articles, and methods generally relate to sampling from an available probability distribution. The samples maybe used to create a desirable probability distribution, for instance for use in computing values used in computational techniques including: Importance Sampling and Markov chain Monte Carlo systems. An analog processor may operate as a sample generator, for example by: programming the analog processor with a configuration of the number of programmable parameters for the analog processor, which corresponds to a probability distribution over qubits of the analog processor, evolving the analog processor with a fast ramp operation, and reading out states for the qubits. The state for the qubits may be post processes and/or used to calculate importance weights.

Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.

Abstract: Systems and methods for magnetic shielding are described. A magnetic shield formed of a material having a high magnetic permeability may be degaussed using a toroidal degaussing coil. The toroidal degaussing coil may enclose at least a portion of the shield. Magnetic field gradients may be actively compensated using multiple magnetic field sensors and local compensation coils. Trapped fluxons may be removed by an application of Lorentz force wherein an electrical current is passed through a superconducting plane.

Abstract: Systems, methods and aspects, and embodiments thereof relate to unsupervised or semi-supervised features learning using a quantum processor. To achieve unsupervised or semi-supervised features learning, the quantum processor is programmed to achieve Hierarchal Deep Learning (referred to as HDL) over one or more data sets. Systems and methods search for, parse, and detect maximally repeating patterns in one or more data sets or across data or data sets. Embodiments and aspects regard using sparse coding to detect maximally repeating patterns in or across data. Examples of sparse coding include L0 and L1 sparse coding. Some implementations may involve appending, incorporating or attaching labels to dictionary elements, or constituent elements of one or more dictionaries. There may be a logical association between label and the element labeled such that the process of unsupervised or semi-supervised feature learning spans both the elements and the incorporated, attached or appended label.

Abstract: Apparatus and methods enable active compensation for unwanted discrepancies in the superconducting elements of a quantum processor. A qubit may include a primary compound Josephson junction (CJJ) structure, which may include at least a first secondary CJJ structure to enable compensation for Josephson junction asymmetry in the primary CJJ structure. A qubit may include a series LC-circuit coupled in parallel with a first CJJ structure to provide a tunable capacitance. A qubit control system may include means for tuning inductance of a qubit loop, for instance a tunable coupler inductively coupled to the qubit loop and controlled by a programming interface, or a CJJ structure coupled in series with the qubit loop and controlled by a programming interface.

Abstract: Methods and systems represent constraint as an Ising model penalty function and a penalty gap associated therewith, the penalty gap separating a set of feasible solutions to the constraint from a set of infeasible solutions to the constraint; and determines the Ising model penalty function subject to the bounds on the programmable parameters imposed by the hardware limitations of the second processor, where the penalty gap exceeds a predetermined threshold greater than zero. Such may be employed to find quantum binary optimization problems and associated gap values employing a variety of techniques.

Abstract: Topologies for analog computing systems are provided. Qubits in the topology are grouped into cells, and cells are coupled to adjacent cells by inter-cell couplers. At least some cells are coupled to non-adjacent cells via long-range couplers. Long-range couplers may be arranged into coverings so that certain sets of qubits within a covering region may be coupled with a reduced number of couplers. Each cell within a covering region without a long-range coupler may be proximate to a cell with a long range coupler so that each cell within the covering region is no more than a certain coupling distance away from a long-range coupler. Long-range couplers may couple over a greater physical distance than inter-cell couplers. Long-range couplers may couple to qubits over a larger coupling region, and may extend across multiple crossing regions between qubits.

Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices. A method of determining a result of a computational problem using an analog processor includes receiving at a first digital computer, including a digital processor, an instance of the computational problem defined over an input graph, wherein the input graph is non-planar; and determining a mapping of the instance of the computational problem onto the analog processor, by the digital processor.

Abstract: Systems and devices for providing differential input/output communication with a superconducting device are described. Each differential I/O communication is electrically filtered using a respective tubular filter structure incorporating superconducting lumped element devices and high frequency dissipation by metal powder epoxy. A plurality of such tubular filter structures is arranged in a cryogenic, multi-tiered assembly further including structural/thermalization supports and a device sample holder assembly for securing a device sample, for example a superconducting quantum processor. The interface between the cryogenic tubular filter assembly and room temperature electronics is achieved using hermetically sealed vacuum feed-through structures designed to receive flexible printed circuit board cable.

Abstract: Systems and methods for employing macroscopic resonant tunneling operations in quantum processors are described. New modes of use for quantum processor architectures employ probe qubits to determine energy eigenvalues of a problem Hamiltonian through macroscopic resonant tunneling operations. A dedicated probe qubit design that may be added to quantum processor architectures is also described. The dedicated probe qubit enables improved performance of macroscopic resonant tunneling operations and, consequently, improved performance of the new modes of use described.

Abstract: A quantum processor is operable as a universal adiabatic quantum computing system. The quantum processor includes physical qubits, with at least a first and second communicative coupling available between pairs of qubits via an in-situ tunable superconducting capacitive coupler and an in-situ tunable superconducting inductive coupler, respectively. Tunable couplers provide diagonal and off-diagonal coupling. Compound Josephson junctions (CJJs) of the tunable couplers are responsive to a flux bias to tune a sign and magnitude of a sum of a capacitance of a fixed capacitor and a tunable capacitance which is mediated across a pair of coupling capacitors. The qubits may be hybrid qubits, operable in a flux regime or a charge regime. Qubits may include a pair of CJJs that interrupt a loop of material and which are separated by an island of superconducting material which is voltage biased with respect to a qubit body.

Abstract: Techniques for improving the performance of a quantum processor are described. The techniques include reading out a fraction of the qubits in a quantum processor and utilizing one or more post-processing operations to reconstruct qubits of the quantum processor that are not read. The reconstructed qubits may be determined using a perfect sampler to provide results that are strictly better than reading all of the qubits directly from the quantum processor. The composite sample that includes read qubits and reconstructed qubits may be obtained faster than if all qubits of the quantum processor are read directly.

Abstract: Systems, devices, articles, methods, and techniques for advancing quantum computing by removing unwanted interactions in one or more quantum processor. One approach includes creating an updated plurality of programmable parameters based at least in part on a received value for the characteristic magnetic susceptibility of the qubit in the at least one quantum processor, and returning the updated plurality of programmable parameters. Examples programmable parameters include local biases, and coupling values characterizing the problem Hamilton.

Abstract: Devices, methods and articles advantageously allow communications between qubits to provide an architecture for universal adiabatic quantum computation. The architecture includes a first coupled basis A1B1 and a second coupled basis A2B2 that does not commute with the first basis A1B1.

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap connector.

Abstract: Computational systems implement problem solving using heuristic solvers or optimizers. Such may iteratively evaluate a result of processing, and modify the problem or representation thereof before repeating processing on the modified problem, until a termination condition is reached. Heuristic solvers or optimizers may execute on one or more digital processors and/or one or more quantum processors. The system may autonomously select between types of hardware devices and/or types of heuristic optimization algorithms. Such may coordinate or at least partially overlap post-processing operations with processing operations, for instance performing post-processing on an ith batch of samples while generating an (i+1)th batch of samples, e.g., so post-processing operation on the ith batch of samples does not extend in time beyond the generation of the (i+1)th batch of samples. Heuristic optimizers selection is based on pre-processing assessment of the problem, e.g.

Abstract: A problem graph having one or more odd cycles is embedded in a quantum processor. The quantum processor includes a plurality of qubits and coupling devices, each coupling device operable to provide controllable communicative coupling between a respective pair of the plurality of qubits to form an interconnected topology. Embedding may, for example, be realized by mapping each vertex of the problem graph to a respective single qubit; mapping each edge of the problem graph to a respective single coupling device, where for pairs of qubits, each qubit of the pair is mapped to a respective pair of vertices. The problem graph may include one or more sub-graphs, one or more of the sub-graphs being a bipartite K3,3 graph.

Abstract: Systems and methods formulate problems for solving by a quantum processor using hardware graph decomposition. A decomposition of a primal graph may be built in a first stage based on a hardware specific graph, and refined in a second stage by, for example, removing vertices from the decomposition. The hardware specific graph may be a graph that is specific to a piece of hardware, for instance a quantum processor comprising a plurality of qubits and couplers operable to communicatively couple pairs of qubits.

Abstract: The effects of decoherence and/or noise in adiabatic quantum computation and quantum annealing are reduced by implementing replica coding schemes. Multiple instances of the same problem are mapped to respective subsets of the qubits and coupling devices of a quantum processor. The multiple instances are evolved simultaneously in the presence of coupling between the qubits of different instances. Quantum processor architectures that are adapted to facilitate replica coding are also described.