Patents Assigned to D-Wave Systems, Inc.
  • Patent number: 11900216
    Abstract: Systems and methods are described for operating a hybrid computing system using cluster contraction for converting large, dense input to reduced input that can be easily mapped into a quantum processor. The reduced input represents the global structure of the problem. Techniques involve partitioning the input variables into clusters and contracting each cluster. The input variables can be partitioned using an Unweighted Pair Group Method with Arithmetic Mean algorithm. The quantum processor returns samples based on the reduced input and the samples are expanded to correspond to the original input.
    Type: Grant
    Filed: November 16, 2022
    Date of Patent: February 13, 2024
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: James A. King, William W. Bernoudy, Kelly T. R. Boothby, Pau Farré Pérez
  • Patent number: 11900264
    Abstract: Hybrid quantum-classical approaches for solving computational problems in which results from a quantum processor are combined with an exact method executed on a classical processor are described. Quantum processors can generate candidate solutions to a combinatorial optimization problem, but since quantum processors can be probabilistic, they are unable to certify that a solution is an optimal solution. A hybrid quantum-classical exact solver addresses this problem by combining outputs from a quantum annealing processor with a classical exact algorithm that is modified to exploit properties of the quantum computation. The exact method executed on a classical processor can be a Branch and Bound algorithm. A Branch and Bound algorithm can be modified to exploit properties of quantum computation including a) the sampling of multiple low-energy solutions by a quantum processor, and b) the embedding of solutions in a regular structure such as a native hardware graph of a quantum processor.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: February 13, 2024
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Catherine McGeoch, William W. Bernoudy
  • Patent number: 11880741
    Abstract: Generate an automorphism of the problem graph, determine an embedding of the automorphism to the hardware graph and modify the embedding of the problem graph into the hardware graph to correspond to the embedding of the automorphism to the hardware graph. Determine an upper-bound on the required chain strength. Calibrate and record properties of the component of a quantum processor with a digital processor, query the digital processor for a range of properties. Generate a bit mask and change the sign of the bias of individual qubits according to the bit mask before submitting a problem to a quantum processor, apply the same bit mask to the bit result. Generate a second set of parameters of a quantum processor from a first set of parameters via a genetic algorithm.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: January 23, 2024
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Robert B. Israel, Trevor M. Lanting, Andrew D. King
  • Patent number: 11879950
    Abstract: Superconducting integrated circuits may advantageously employ superconducting resonators coupled to a microwave transmission line to efficiently address superconducting flux storage devices. In an XY-addressing scheme, a global flux bias may be applied to a number of superconducting flux storage devices via a low-frequency address line, and individual superconducting flux storage devices addressed via application of high-frequency pulses via resonators driven by the microwave transmission line. Frequency multiplexing can be employed to provide signals to two or more resonators. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to provide Z-addressing. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to eliminate a flux bias line.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: January 23, 2024
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Loren J. Swenson, Emile M. Hoskinson, Mark H. Volkmann, Andrew J. Berkley, George E. G. Sterling, Jed D. Whittaker
  • Patent number: 11874344
    Abstract: A device is dynamically isolated via a broadband switch that includes a plurality of cascade elements in series, wherein each cascade element comprises a first set of SQUIDs in series, a matching capacitor, and a second set of SQUIDs in series. The broadband switch is set to a passing state via flux bias lines during programming and readout of the device and set to a suppression state during device's calculation to reduce operation errors at the device. A device is electrically isolated from high-frequencies via an unbiased broadband switch. A device is coupled to a tunable thermal bath that includes a broadband switch.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: January 16, 2024
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Loren J. Swenson, Andrew J. Berkley, Mark H. Volkmann, George E. G. Sterling, Jed D. Whittaker
  • Patent number: 11861455
    Abstract: A computational method via a hybrid processor comprising an analog processor and a digital processor includes determining a first classical spin configuration via the digital processor, determining preparatory biases toward the first classical spin configuration, programming an Ising problem and the preparatory biases in the analog processor via the digital processor, evolving the analog processor in a first direction, latching the state of the analog processor for a first dwell time, programming the analog processor to remove the preparatory biases via the digital processor, determining a tunneling energy via the digital processor, determining a second dwell time via the digital processor, evolving the analog processor in a second direction until the analog processor reaches the tunneling energy, and evolving the analog processor in the first direction until the analog processor reaches a second classical spin configuration.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: January 2, 2024
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Sheir Yarkoni, Trevor Michael Lanting, Kelly T. R. Boothby, Andrew Douglas King, Evgeny A. Andriyash, Mohammad H. Amin
  • Patent number: 11856871
    Abstract: Systems and methods for fabricating a superconducting integrated circuit that includes wiring layers comprising low-noise material are described. A superconducting integrated circuit can be implemented in a computing system that includes a quantum processor. Such a superconducting integrated circuit includes a first set of one or more wiring layers that form a noise-susceptible superconducting device that can decrease processor when exposed to noise. The superconducting integrated circuit can further include a second set of one or more wiring layers that form a superconducting device that is less susceptible to noise. Fabricating a superconducting device that contains low-noise material can include depositing and patterning a wiring layer comprising a first material that is superconductive in a respective range of temperatures and depositing and patterning a different wiring layer comprising a second material that is superconductive in a respective range of temperatures.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: December 26, 2023
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Trevor M. Lanting, Danica W. Marsden, Byong Hyop Oh, Eric G. Ladizinsky, Shuiyuan Huang, J. Jason Yao, Douglas P. Stadtler
  • Patent number: 11847534
    Abstract: A superconducting readout system employing a microwave transmission line, and a microwave superconducting resonator communicatively coupled to the microwave transmission line, and including a superconducting quantum interference device (SQUID), may be advantageously calibrated at least in part by measuring a resonant frequency of the microwave superconducting resonator in response to a flux bias applied to the SQUID, measuring a sensitivity of the resonant frequency in response to the flux bias, and selecting an operating frequency and a sensitivity of the microwave superconducting resonator based at least in part on a variation of the resonant frequency as a function of the flux bias. The flux bias may be applied to the SQUID by an interface inductively coupled to the SQUID. Calibration of the superconducting readout system may also include determining at least one of a propagation delay, a microwave transmission line delay, and a microwave transmission line phase offset.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: December 19, 2023
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Jed D. Whittaker, Loren J. Swenson, Ilya V. Perminov, Abraham J. Evert, Peter D. Spear, Mark H. Volkmann, Catia Baron Aznar, Michael S. Babcock
  • Patent number: 11839164
    Abstract: Addressing a superconducting flux storage device may include applying a bias current, a low-frequency flux bias, and a high-frequency flux bias in combination to cause a combined address signal level to exceed a defined address signal latching level for the superconducting flux storage device. A bias current that, in combination with a low-frequency flux bias and a high-frequency flux bias, causes a combined address signal level to exceed a defined address signal latching level for a superconducting flux storage device is at least reduced by an asymmetry in the Josephson junctions of the CJJ. A low-frequency flux bias that, in combination with a bias current and a high-frequency flux bias, causes a combined address signal level to exceed a defined address signal latching level for a superconducting flux storage device is at least reduced by an asymmetry in the Josephson junctions of the CJJ.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: December 5, 2023
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Loren J. Swenson, George E. G. Sterling, Christopher B. Rich
  • Patent number: 11836574
    Abstract: Achieving orthogonal control of non-orthogonal qubit parameters of a logical qubit allows for increasing the length of a qubit chain thereby increasing the effective connectivity of the qubit chain. A hybrid qubit is formed by communicatively coupling a dedicated second qubit to a first qubit. By tuning a programmable parameter of the second qubit of a hybrid qubit, an effective programmable parameter of the hybrid qubit is adjusted without affecting another effective programmable parameter of the hybrid qubit thereby achieving orthogonal control of otherwise non-orthogonal qubit parameters. The length of the logical qubit may thus be increased by communicatively coupling a plurality of such hybrid qubits together.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: December 5, 2023
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Mohammad H. S. Amin, Trevor Michael Lanting, Colin Enderud
  • Patent number: 11790259
    Abstract: Quantum processors having qubits with tunable capacitance are provided. The qubits include Josephson junctions shunted by capacitors and are tunably coupled to capacitance loops such that the resonant frequencies of the qubits and capacitance loops avoid entanglement with each other. Methods for tuning the capacitance of such qubits by varying the coupler's coupling strength are provided. These methods include methods for calibrating qubits' capacitance.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: October 17, 2023
    Assignee: D-WAVE SYSTEMS INC.
    Inventor: Richard G. Harris
  • Patent number: 11714730
    Abstract: Systems, methods and article provide the services of heterogeneous resources, for example the services analog processors, e.g., quantum processors, in a robust manner that can include high availability, failover, and load balancing of the heterogeneous resources. A virtual solver is selected based at least in part on a first set of requirements, a first set of analog processors is identified based at least in part on the first set of requirements, and a first handle returned to the first virtual solver. A load balancer may balance loads. Failure over may be implemented.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: August 1, 2023
    Assignee: D-WAVE SYSTEMS INC.
    Inventor: Radomir Stevanovic
  • Patent number: 11704586
    Abstract: Computational systems implement problem solving using hybrid digital/quantum computing approaches. A problem may be represented as a problem graph which is larger and/or has higher connectivity than a working and/or hardware graph of a quantum processor. A quantum processor may be used determine approximate solutions, which solutions are provided as initial states to one or more digital processors which may implement classical post-processing to generate improved solutions. Techniques for solving problems on extended, more-connected, and/or “virtual full yield” variations of the processor's actual working and/or hardware graphs are provided. A method of operation in a computational system comprising a quantum processor includes partitioning a problem graph into sub-problem graphs, and embedding a sub-problem graph onto the working graph of the quantum processor. The quantum processor and a non-quantum processor-based device generate partial samples.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: July 18, 2023
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Murray C. Thom, Aidan P. Roy, Fabian A. Chudak, Zhengbing Bian, William G. Macready, Robert B. Israel, Kelly T. R. Boothby, Sheir Yarkoni, Yanbo Xue, Dmytro Korenkevych
  • Patent number: 11704012
    Abstract: A user interface (UI), data structures and algorithms facilitate programming, analyzing, debugging, embedding, and/or modifying problems that are embedded or to be embedded on an analog processor (e.g., quantum processor), increasing computational efficiency and/or accuracy of problem solutions. The UI provides graph representations (e.g., source graph, target graph and correspondence therebetween) with nodes and edges which may map to hardware components (e.g., qubits, couplers) of the analog processor. Characteristics of solutions are advantageously represented spatially associated (e.g., overlaid or nested) with characteristics of a problem. Characteristics (e.g., bias state) may be represented by color, pattern, values, icons. Issues (e.g., broken chains) may be detected and alerts provided.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: July 18, 2023
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Murray C. Thom, Fiona L. Hanington, Alexander Condello, William W. Bernoudy, Melody C. Wong, Aidan P. Roy, Kelly T. R. Boothby, Edward D. Dahl
  • Patent number: 11678433
    Abstract: Systems, methods, and devices for electrically coupling an integrated circuit to a set of coaxial lines via a printed circuit board assembly are described. A device sample holder includes a printed circuit board that is operable to edge-couple to an integrated circuit. A surface of the printed circuit board that carries a set of coaxial connectors is orthogonal to another surface of the printed circuit board that exposes a set of conductive traces. The set of conductive traces are operable to electrically couple to a set of conductive paths of an integrated circuit to provide a communicative path between the integrated circuit and components of an input/output system in a refrigerated environment.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: June 13, 2023
    Assignee: D-WAVE SYSTEMS INC.
    Inventor: Richard D. Neufeld
  • Patent number: 11663512
    Abstract: Computational systems and methods employ characteristics of a quantum processor determined or sampled between a start and an end of an annealing evolution per an annealing schedule. The annealing evolution can be reinitialized, reversed or continued after determination. The annealing evolution can be interrupted. The annealing evolution can be ramped immediately prior to or as part of determining the characteristics. The annealing evolution can be paused or not paused immediately prior to ramping. A second representation of a problem can be generated based at least in part on the determined characteristics from an annealing evolution performed on a first representation of the problem. The determined characteristics can be autonomously compared to an expected behavior, and alerts optionally provided and/or the annealing evolution optionally terminated based on the comparison. Iterations of annealing evolutions may be performed until an exit condition occurs.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: May 30, 2023
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Steven P. Reinhardt, Andrew D. King, Loren J. Swenson, Warren T. E. Wilkinson, Trevor Michael Lanting
  • Patent number: 11647590
    Abstract: A method of fabricating a multilayer superconducting printed circuit board comprises first, forming a bimetal foil to overlie a substrate, the bimetal foil comprising a first layer of a first metal, a layer of a second metal, and a second layer of the first metal, and then etching the second layer of the first metal. Forming a bimetal foil to overlie a substrate may include forming a bimetal foil comprising a first layer of a normal metal, a layer of a superconducting metal, and a second layer of the normal metal. Etching the second layer of the first metal may include preparing a patterned image in the second layer of the first metal for etching, processing the patterned image through a cleaner, rinsing the patterned image, and then, immersing the patterned image in a microetch.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: May 9, 2023
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Jeffrey P. Burress, Richard D. Neufeld, Surjit Singh Dhesi
  • Patent number: 11625612
    Abstract: The domain adaptation problem is addressed by using the predictions of a trained model over both source and target domain to retain the model with the assistance of an auxiliary model and a modified objective function. Inaccuracy in the model's predictions in the target domain is treated as noise and is reduced by using a robust learning framework during retraining, enabling unsupervised training in the target domain. Applications include object detection models, where noise in retraining is reduced by explicitly representing label noise and geometry noise in the objective function and using the ancillary model to inject information about label noise.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: April 11, 2023
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Arash Vahdat, Mani Ranjbar, Mehran Khodabandeh, William G. Macready, Zhengbing Bian
  • Patent number: 11617272
    Abstract: A multilayer circuit board structure includes superconducting connections to internal layers thereof, for example by inclusion of superconducting vias. Two or more panels can each comprise respective electrically insulative substrates, each have one or more through-holes, and also include a respective bimetal foil on at least a portion of a respective surface thereof, which is patterned to form traces. The bimetal foil includes a first metal that is non-superconductive in a first temperature range and a second metal that is superconductive in the first temperature range. The panels are plated to deposit a third metal on exposed traces of the second metal, the third metal superconductive in the first temperature range. Panels are join (e.g., laminated) to form at least a three-layer superconducting printed circuit board with an inner layer, two outer layers, and superconducting vias between the inner layer and at least one of the two outer layers.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: March 28, 2023
    Assignee: D-WAVE SYSTEMS INC.
    Inventor: Richard D. Neufeld
  • Patent number: D1002664
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: October 24, 2023
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Fiona L. Hanington, Murray C. Thom, Dominic Wong, Jeffrey P. Johnston, Skyler J. Richter