Patents Assigned to D-Wave Systems, Inc.
  • Patent number: 11617272
    Abstract: A multilayer circuit board structure includes superconducting connections to internal layers thereof, for example by inclusion of superconducting vias. Two or more panels can each comprise respective electrically insulative substrates, each have one or more through-holes, and also include a respective bimetal foil on at least a portion of a respective surface thereof, which is patterned to form traces. The bimetal foil includes a first metal that is non-superconductive in a first temperature range and a second metal that is superconductive in the first temperature range. The panels are plated to deposit a third metal on exposed traces of the second metal, the third metal superconductive in the first temperature range. Panels are join (e.g., laminated) to form at least a three-layer superconducting printed circuit board with an inner layer, two outer layers, and superconducting vias between the inner layer and at least one of the two outer layers.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: March 28, 2023
    Assignee: D-WAVE SYSTEMS INC.
    Inventor: Richard D. Neufeld
  • Patent number: 11593174
    Abstract: Systems and methods for scheduling usage time for programs that can be executed on a hybrid computing system including a quantum processing unit (QPU) and a central processing unit (CPU). Programs can comprise both QPU-executable tasks and CPU-executable tasks. Some programs can be considered high performance programs that are intolerant of interruptions to QPU-executable tasks and some programs can be considered low performance programs that are tolerant of interruptions to QPU-executable tasks. After a high performance program finishes executing QPU-executable tasks on a QPU, a low performance program may execute QPU-executable tasks on the QPU while the high performance program executes CPU-executable tasks on a CPU. Execution of QPU-executable tasks of a low performance program on a QPU can pause or stop if a high performance program is queued.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: February 28, 2023
    Assignee: D-WAVE SYSTEMS INC.
    Inventor: Steven P. Reinhardt
  • Patent number: 11593695
    Abstract: A hybrid computing system for solving a computational problem includes a digital processor, a quantum processor having qubits and coupling devices that together define a working graph of the quantum processor, and at least one nontransitory processor-readable medium communicatively coupleable to the digital processor which stores at least one of processor-executable instructions or data. The digital processor receives a computational problem, and programs the quantum processor with a first set of bias fields and a first set of coupling strengths. The quantum processor generates samples as potential solutions to an approximation of the problem. The digital processor updates the approximation by determining a second set of bias fields based at least in part on the first set of bias fields and a first set of mean fields that are based at least in part on the first set of samples and coupling strengths of one or more virtual coupling devices.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: February 28, 2023
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: William W. Bernoudy, Mohammad H. Amin, James A. King, Jeremy P. Hilton, Richard G. Harris, Andrew J. Berkley, Kelly T. R. Boothby
  • Patent number: 11586915
    Abstract: Collaborative filtering systems based on variational autoencoders (VAEs) are provided. VAEs may be trained on row-wise data without necessarily training a paired VAE on column-wise data (or vice-versa), and may optionally be trained via minibatches. The row-wise VAE models the output of the corresponding column-based VAE as a set of parameters and uses these parameters in decoding. In some implementations, a paired VAE is provided which receives column-wise data and models row-wise parameters; each of the paired VAEs may bind their learned column- or row-wise parameters to the output of the corresponding VAE. The paired VAEs may optionally be trained via minibatches. Unobserved data may be explicitly modelled. Methods for performing inference with such VAE-based collaborative filtering systems are also disclosed, as are example applications to search and anomaly detection.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: February 21, 2023
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: William G. Macready, Jason T. Rolfe
  • Patent number: 11567779
    Abstract: A highly parallelized parallel tempering technique for simulating dynamic systems, such as quantum processors, is provided. Replica exchange is facilitated by synchronizing grid-level memory. Particular implementations for simulating quantum processors by representing cells of qubits and couplers in grid-, block-, and thread-level memory are discussed. Parallel tempering of such dynamic systems can be assisted by modifying replicas based on isoenergetic cluster moves (ICMs). ICMs are generated via secondary replicas which are maintained alongside primary replicas and exchanged between blocks and/or generated dynamically by blocks without necessarily being exchanged. Certain refinements, such as exchanging energies and temperatures through grid-level memory, are also discussed.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: January 31, 2023
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: William W. Bernoudy, James A. King, Andrew D. King
  • Patent number: 11561269
    Abstract: A device is dynamically isolated via a broadband switch that includes a plurality of cascade elements in series, wherein each cascade element comprises a first set of SQUIDs in series, a matching capacitor, and a second set of SQUIDs in series. The broadband switch is set to a passing state via flux bias lines during programming and readout of the device and set to a suppression state during device's calculation to reduce operation errors at the device. A device is electrically isolated from high-frequencies via an unbiased broadband switch. A device is coupled to a tunable thermal bath that includes a broadband switch.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: January 24, 2023
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Loren J. Swenson, Andrew J. Berkley, Mark H. Volkmann, George E. G. Sterling, Jed D. Whittaker
  • Patent number: 11537926
    Abstract: Systems and methods are described for operating a hybrid computing system using cluster contraction for converting large, dense input to reduced input that can be easily mapped into a quantum processor. The reduced input represents the global structure of the problem. Techniques involve partitioning the input variables into clusters and contracting each cluster. The input variables can be partitioned using an Unweighted Pair Group Method with Arithmetic Mean algorithm. The quantum processor returns samples based on the reduced input and the samples are expanded to correspond to the original input.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: December 27, 2022
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: James A. King, William W. Bernoudy, Kelly T. R. Boothby, Pau Farré Pérez
  • Patent number: 11531852
    Abstract: Machine learning classification models which are robust against label noise are provided. Noise may be modelled explicitly by modelling “label flips”, where incorrect binary labels are “flipped” relative to their ground truth value. Distributions of label flips may be modelled as prior and posterior distributions in a flexible architecture for machine learning systems. An arbitrary classification model may be provided within the system. The classification model is made more robust to label noise by operation of the prior and posterior distributions. Particular prior and approximating posterior distributions are disclosed.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: December 20, 2022
    Assignee: D-WAVE SYSTEMS INC.
    Inventor: Arash Vahdat
  • Patent number: 11526463
    Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: December 13, 2022
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Alexander Maassen van den Brink, Peter Love, Mohammad H. S. Amin, Geordie Rose, David Grant, Miles F. H. Steininger, Paul I. Bunyk, Andrew J. Berkley
  • Patent number: 11514223
    Abstract: Systems and methods are described to accurately extract device parameters and optimize the design of macroscopic superconducting structures, for example qubits. This method presents the advantage of reusing existing plaquettes to simulate different processor topologies. The physical elements of a qubits are extracted via plurality of plaquettes. Each plaquette contains at least one physical element of the qubit design and has two ports on each side. Each plaquette is concatenated to at least one other plaquette via two ports. The values of inductance (L), capacitance (C) and mutual inductance (M) and quantum critical point of the qubit design can be computed. Changing the physical elements of the qubit design and iterating the method allows to effortlessly refine the qubit design.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: November 29, 2022
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Reza Molavi, Mark H. Volkmann, Paul I. Bunyk
  • Patent number: 11507871
    Abstract: Topologies for analog computing systems may include cells of qubits which may implement a tripartite graph and cross substantially orthogonally. Qubits may have an H-shape or an l-shape, qubits may change direction within a cell. Topologies may be comprised of two or more different sub-topologies. Qubits may be communicatively coupled to non-adjacent cells by long-range couplers. Long-range couplers may change direction within a cell. A cell may have two or more different type of long-range couplers. A cell may have shifted qubits, more than one type of inter-cell couplers, more than one type of intra-cell couplers and long-range couplers.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: November 22, 2022
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Kelly T. R. Boothby, Paul I. Bunyk
  • Patent number: 11501195
    Abstract: Systems, methods and aspects, and embodiments thereof relate to unsupervised or semi-supervised features learning using a quantum processor. To achieve unsupervised or semi-supervised features learning, the quantum processor is programmed to achieve Hierarchal Deep Learning (referred to as HDL) over one or more data sets. Systems and methods search for, parse, and detect maximally repeating patterns in one or more data sets or across data or data sets. Embodiments and aspects regard using sparse coding to detect maximally repeating patterns in or across data. Examples of sparse coding include L0 and L1 sparse coding. Some implementations may involve appending, incorporating or attaching labels to dictionary elements, or constituent elements of one or more dictionaries. There may be a logical association between label and the element labeled such that the process of unsupervised or semi-supervised feature learning spans both the elements and the incorporated, attached or appended label.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: November 15, 2022
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Geordie Rose, Suzanne Gildert, William G. Macready, Dominic Christoph Walliman
  • Patent number: 11494683
    Abstract: Josephson junctions (JJ) may replace primary inductance of transformers to realize galvanic coupling between qubits, advantageously reducing size. A long-range symmetric coupler may include a compound JJ (CJJ) positioned at least approximately at a half-way point along the coupler to advantageously provide a higher energy of a first excited state than that of an asymmetric long-range coupler. Quantum processors may include qubits and couplers with a non-stoquastic Hamiltonian to enhance multi-qubit tunneling during annealing. Qubits may include additional shunt capacitances, e.g., to increase overall quality of a total capacitance and improve quantum coherence. A sign and/or magnitude of an effective tunneling amplitude ?eff of a qubit characterized by a double-well potential energy may advantageously be tuned. Sign-tunable electrostatic coupling of qubits may be implemented, e.g., via resonators, and LC-circuits. YY couplings may be incorporated into a quantum anneaier (e.g., quantum processor).
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: November 8, 2022
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Mohammad H. Amin, Paul I. Bunyk, Trevor M. Lanting, Chunqing Deng, Anatoly Smirnov, Kelly T. R. Boothby, Emile M. Hoskinson, Christopher B. Rich
  • Patent number: 11481669
    Abstract: A digital processor runs a machine learning algorithm in parallel with a sampling server. The sampling sever may continuously or intermittently draw samples for the machine learning algorithm during execution of the machine learning algorithm, for example on a given problem. The sampling server may run in parallel (e.g., concurrently, overlapping, simultaneously) with a quantum processor to draw samples from the quantum processor.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: October 25, 2022
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Jason T. Rolfe, William G. Macready, Mani Ranjbar, Mayssam Mohammad Nevisi
  • Patent number: 11481354
    Abstract: A hybrid computing system comprising a digital and an analog processor calculates the ground energy state of a non-diagonal Hamiltonian via diagonalization of the Hamiltonian in different bases and reverse annealing. A first basis is rotated to render part of the Hamiltonian diagonal, then the quantum processor evolves backwards until a value s* of the normalized evolution coefficient. Another basis is rotated to render another part of the Hamiltonian diagonal and the quantum processor evolves backwards again until s*. The bases can be rotated via discrete Fourier transform. The quantum processor may pause for a time t after each backward evolution. The ground state energy is calculated using the final ground states.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: October 25, 2022
    Assignee: D-WAVE SYSTEMS INC.
    Inventor: A. Isil Ozfidan
  • Patent number: 11468293
    Abstract: A hybrid computing system comprising a quantum computer and a digital computer employs a digital computer to use machine learning methods for post-processing samples drawn from the quantum computer. Post-processing samples can include simulating samples drawn from the quantum computer. Machine learning methods such as generative adversarial networks (GANs) and conditional GANs are applied. Samples drawn from the quantum computer can be a target distribution. A generator of a GAN generates samples based on a noise prior distribution and a discriminator of a GAN measures the distance between the target distribution and a generative distribution. A generator parameter and a discriminator parameter are respectively minimized and maximized.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: October 11, 2022
    Assignee: D-WAVE SYSTEMS INC.
    Inventor: Fabian A. Chudak
  • Patent number: 11461644
    Abstract: Fully-supervised semantic segmentation machine learning models are augmented by ancillary machine learning models which generate high-detail predictions from low-detail, weakly-supervised data. The combined model can be trained over both fully- and weakly-supervised data. Only the primary model is required for inference, post-training. The combined model can be made self-correcting during training by adjusting the ancillary model's output based on parameters learned over both the fully- and weakly-supervised data. The self-correction module may combine the output of the primary and ancillary models in various ways, including through linear combinations and via neural networks. The self-correction module and ancillary model may benefit from disclosed pre-training techniques.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: October 4, 2022
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Arash Vahdat, Mostafa S. Ibrahim, William G. Macready
  • Patent number: 11449784
    Abstract: In many cases after degaussing the field distribution in a magnetic material there may be regions within the magnetic material that have ordered domains that contribute a remnant field. There is the need to reduce or eliminate non-uniform fields within a volume of interest left after degaussing a magnetic shield. Degaussing coils surrounding a metal shield can be used to favorably order magnetic domains within the material to counteract the remnant fields left behind following imperfect degaussing. The remnant field value can be measured and a small current may be applied through the degaussing coils. After removing the current, the field can be measured again and a higher current may be applied again through the coils. Repeated applications of currents and field measurement will progressively order domains in the direction of the applied field, resulting in a reduction of the net field and lower field gradient across the volume of interest.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: September 20, 2022
    Assignee: D-WAVE SYSTEMS INC.
    Inventor: George E. G. Sterling
  • Patent number: 11422958
    Abstract: A quantum processor performs input and output which may be performed synchronously. The quantum processor executes a problem to generate a classical output state, which is read out at least partially by an I/O system. The I/O system also transmits a classical input state to by the I/O system, which may include the same qubit-proximate devices used for read-out. The classical input state is written to the qubits, and the quantum processor executes based on the classical input state (e.g., by performing reverse annealing to transform the classical input state to quantum state).
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: August 23, 2022
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Kelly T.R. Boothby, Andrew J. Berkley, Christopher B. Rich
  • Patent number: 11423115
    Abstract: Systems, devices, articles, methods, and techniques for advancing quantum computing by removing unwanted interactions in one or more quantum processor. One approach includes creating an updated plurality of programmable parameters based at least in part on a received value for the characteristic magnetic susceptibility of the qubit in the at least one quantum processor, and returning the updated plurality of programmable parameters. Examples programmable parameters include local biases, and coupling values characterizing the problem Hamilton.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: August 23, 2022
    Assignee: D-WAVE SYSTEMS INC.
    Inventor: Trevor Michael Lanting