Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.

Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a multiplication circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A multiplication circuit may employ binary representations of factors, and these binary representations may be decomposed to reduce the total number of variables required to represent the multiplication circuit.

Abstract: Quantum annealing may include applying and gradually removing disorder terms to qubits of a quantum processor, for example superconducting flux qubits of a superconducting quantum processor. A problem Hamiltonian may be established by applying control signals to the qubits, an evolution Hamiltonian established by applying disorder terms, and annealing by gradually removing the disorder terms. Change in persistent current in the qubits may be compensated. Multipliers may mediate coupling between various qubits and a global signal line, for example by applying respective scaling factors. Two global signal lines may be arranged in an interdigitated pattern to couple to respective qubits of a communicatively coupled pair of qubits. Pairs of qubits may be communicatively isolated and used to measure a response of one another to defined signals.

Abstract: Methods for solving a computational problem including minimizing an objective including a set of weights and a dictionary by casting the weights as Boolean variables and alternately using a quantum processor and a non-quantum processor to successively optimize the weights and the dictionary, respectively. A first set of values for the dictionary is guessed and the objective is mapped to a QUBO. A quantum processor is used to optimize the objective for the Boolean weights based on the first set of values for the dictionary by minimizing the resulting QUBO. A non-quantum processor is used to optimize the objective for the dictionary based on the Boolean weights by updating at least some of the columns of the dictionary. These processes are successively repeated until a solution criterion is met. Minimization of the objective may be used to generate features in a learning problem and/or in data compression.

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap contact connector.

Abstract: Computational techniques for mapping a continuous variable objective function into a discrete variable objective function problem that facilitate determining a solution of the problem via a quantum processor are described. The modified objective function is solved by minimizing the cost of the mapping via an iterative search algorithm.

Abstract: A system may include first and second qubits that cross one another and a first coupler having a perimeter that encompasses at least a part of the portions of the first and second qubits, the first coupler being operable to ferromagnetically or anti-ferromagnetically couple the first and the second qubits together. A multi-layered computer chip may include a first plurality N of qubits laid out in a first metal layer, a second plurality M of qubits laid out at least partially in a second metal layer that cross each of the qubits of the first plurality of qubits, and a first plurality N times M of coupling devices that at least partially encompasses an area where a respective pair of the qubits from the first and the second plurality of qubits cross each other.

Abstract: Systems and methods for improving the performance of dilution refrigeration systems include cryocondensation traps employed in the helium circuit of a dilution refrigerator may be modified to improve performance. A cryocondensation trap employs a cryocondensation surface having at least one temperature that preferably matches the temperature at which at least one contaminant freezes into a solid form from a gaseous form. A single trap with at least one continuous cryocondensation surface formed in a generally helical or spiral-like fashion with each region having a different temperature may be employed to trap a specific contaminant or set of contaminants. A single trap with multiple cryocondensation surfaces where each surface has a different temperature may be alternatively employed for the same purpose. To provide a temperature gradient in the cryocondensation trap, at least one region of the cryocondensation trap may be thermally coupled to a cold surface and/or a transfer tube.

Abstract: Systems and methods formulate problems for solving by a quantum processor using hardware graph decomposition. A decomposition of a primal graph may be built in a first stage based on a hardware specific graph, and refined in a second stage by, for example, removing vertices from the decomposition. The hardware specific graph may be a graph that is specific to a piece of hardware, for instance a quantum processor comprising a plurality of qubits and couplers operable to communicatively couple pairs of qubits.

Abstract: Systems, devices, and methods for using an analog processor to solve computational problems. A digital processor is configured to track computational problem processing requests received from a plurality of different users, and to track at least one of a status and a processing cost for each of the computational problem processing requests. An analog processor, for example a quantum processor, is operable to assist in producing one or more solutions to computational problems identified by the computational problem processing requests via a physical evolution.

Abstract: Systems and methods for reading out the states of superconducting flux qubits may couple magnetic flux representative of a qubit state to a DC-SQUID in a variable transformer circuit. The DC-SQUID is electrically coupled in parallel with a primary inductor such that a time-varying (e.g., AC) drive current is divided between the DC-SQUID and the primary inductor in a ratio that is dependent on the qubit state. The primary inductor is inductively coupled to a secondary inductor to provide a time-varying (e.g., AC) output signal indicative of the qubit state without causing the DC-SQUID to switch into a voltage state. Coupling between the superconducting flux qubit and the DC-SQUID may be mediated by a routing system including a plurality of latching qubits. Multiple superconducting flux qubits may be coupled to the same routing system so that a single variable transformer circuit may be used to measure the states of multiple qubits.

Abstract: Superconductive interconnection structures providing continuous, uninterrupted superconducting signal paths between a superconducting chip and a superconducting chip carrier are described. The superconductive interconnection structures employ superconducting solder bumps and pillars of Under Bump Metal (“UBM”). The superconductive interconnection structures are employed in a two-stage solder bumping process in which the superconducting chip is first bonded to a testing module for screening and then bonded to a chip packaging module for operation. Either the testing module or the chip packaging module, or both, may include a multi-chip module for carrying multiple superconducting chips simultaneously.

Abstract: Systems and methods allow formulation of embeddings of problems via targeted hardware (e.g., particular quantum processor). In a first stage, sets of connected subgraphs are successively generated, each set including a respective subgraph for each decision variable in the problem graph, adjacent decisions variables in the problem graph mapped to respective vertices in the hardware graph, the respective vertices which are connected by at least one respective edge in the hardware graph. In a second stage, the connected subgraphs are refined such that no vertex represents more than a single decision variable.

Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a Boolean logic circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A quantum processor may include multiple sets of qubits, each set coupled to respective annealing signal lines such that dynamic evolution of each set of qubits is controlled independently from the dynamic evolutions of the other sets of qubits.

Abstract: SQUIDs may detect local magnetic fields. SQUIDS of varying sizes, and hence sensitivities may detect different magnitudes of magnetic fields. SQUIDs may be oriented to detect magnetic fields in a variety of orientations, for example along an orthogonal reference frame of a chip or wafer. The SQUIDS may be formed or carried on the same chip or wafer as a superconducting processor (e.g., a superconducting quantum processor). Measurement of magnetic fields may permit compensation, for example allowing tuning of a compensation field via a compensation coil and/or a heater to warm select portions of a system. A SQIF may be implemented as a SQUID employing an unconventional grating structure. Successful fabrication of an operable SQIF may be facilitated by incorporating multiple Josephson junctions in series in each arm of the unconventional grating structure.

Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.

Abstract: Systems and methods for improving calibration procedures in a quantum processor architecture are described. For example, a dedicated calibration signal source is built into the architecture of the quantum processor for use during calibration. A single calibration signal source is communicatively coupled to many devices in the quantum processor architecture to provide an absolute calibration signal against which various parameters, responses, and/or behaviors of the many devices may be calibrated, either in series or in parallel. The use of a calibration signal source may reduce the time required to calibrate the elements of a quantum processor and/or improve the accuracy/precision of such calibrations.

Abstract: The effects of decoherence and/or noise in adiabatic quantum computation and quantum annealing are reduced by implementing replica coding schemes. Multiple instances of the same problem are mapped to respective subsets of the qubits and coupling devices of a quantum processor. The multiple instances are evolved simultaneously in the presence of coupling between the qubits of different instances. Quantum processor architectures that are adapted to facilitate replica coding are also described.

Abstract: Systems and methods for integrating quantum computing systems into mobile systems for the purpose of providing real-time, quantum computer-based control of the mobile systems are described. A mobile system includes a data extraction subsystem that extracts data from an external environment of the mobile system and a quantum computing subsystem that receives data from the data extraction subsystem and performs a quantum computing operation in real-time using the data from the data extraction subsystem. A result of the quantum computing operation influences a behavior of the mobile system, such as the navigation of the mobile system or an action performed by the mobile system. The on-board quantum computing subsystem includes on-board quantum computing infrastructure that is adapted to suit the needs and spatial constraints of the mobile system.

Abstract: A superconducting flux digital-to-analog converter includes a superconducting inductor ladder circuit. The ladder circuit includes a plurality of closed superconducting current paths that each includes at least two superconducting inductors coupled in series to form a respective superconducting loop, successively adjacent or neighboring superconducting loops are connected in parallel with each other and share at least one of the superconducting inductors to form a flux divider network. A data signal input structure provides a respective bit of a multiple bit signal to each of the superconducting loops. The data signal input structure may include a set of superconducting quantum interference devices (SQUIDs). The data signal input structure may include a superconducting shift register, for example a single-flux quantum (SFQ) shift register or a flux-based superconducting shift register comprising a number of latching qubits.