Abstract: A computational method via a hybrid processor comprising an analog processor and a digital processor includes determining a first classical spin configuration via the digital processor, determining preparatory biases toward the first classical spin configuration, programming an Ising problem and the preparatory biases in the analog processor via the digital processor, evolving the analog processor in a first direction, latching the state of the analog processor for a first dwell time, programming the analog processor to remove the preparatory biases via the digital processor, determining a tunneling energy via the digital processor, determining a second dwell time via the digital processor, evolving the analog processor in a second direction until the analog processor reaches the tunneling energy, and evolving the analog processor in the first direction until the analog processor reaches a second classical spin configuration.

Abstract: The systems, devices, articles, and methods generally relate to sampling from an available probability distribution. The samples maybe used to create a desirable probability distribution, for instance for use in computing values used in computational techniques including: Importance Sampling and Markov chain Monte Carlo systems. An analog processor may operate as a sample generator, for example by: programming the analog processor with a configuration of the number of programmable parameters for the analog processor, which corresponds to a probability distribution over qubits of the analog processor, evolving the analog processor with a fast ramp operation, and reading out states for the qubits. The state for the qubits may be post processes and/or used to calculate importance weights.

Abstract: Techniques for improving the performance of a quantum processor are described. The techniques include reading out a fraction of the qubits in a quantum processor and utilizing one or more post-processing operations to reconstruct qubits of the quantum processor that are not read. The reconstructed qubits may be determined using a perfect sampler to provide results that are strictly better than reading all of the qubits directly from the quantum processor. The composite sample that includes read qubits and reconstructed qubits may be obtained faster than if all qubits of the quantum processor are read directly.

Abstract: Computational systems implement problem solving using hybrid digital/quantum computing approaches. A problem may be represented as a problem graph which is larger and/or has higher connectivity than a working and/or hardware graph of a quantum processor. A quantum processor may be used determine approximate solutions, which solutions are provided as initial states to one or more digital processors which may implement classical post-processing to generate improved solutions. Techniques for solving problems on extended, more-connected, and/or “virtual full yield” variations of the processor's actual working and/or hardware graphs are provided. A method of operation in a computational system comprising a quantum processor includes partitioning a problem graph into sub-problem graphs, and embedding a sub-problem graph onto the working graph of the quantum processor. The quantum processor and a non-quantum processor-based device generate partial samples.

Abstract: Systems and methods for employing macroscopic resonant tunneling operations in quantum processors are described. New modes of use for quantum processor architectures employ probe qubits to determine energy eigenvalues of a problem Hamiltonian through macroscopic resonant tunneling operations. A dedicated probe qubit design that may be added to quantum processor architectures is also described. The dedicated probe qubit enables improved performance of macroscopic resonant tunneling operations and, consequently, improved performance of the new modes of use described.

Abstract: Techniques for improving the performance of a quantum processor are described. Some techniques employ reducing intrinsic/control errors by using quantum processor-wide problems specifically crafted to reveal errors so that corrections may be applied. Corrections may be applied to physical qubits, logical qubits, and couplers so that problems may be solved using quantum processors with greater accuracy.

Abstract: Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures.

Abstract: Systems, devices, articles, methods, and techniques for advancing quantum computing by removing unwanted interactions in one or more quantum processor. One approach includes creating an updated plurality of programmable parameters based at least in part on a received value for the characteristic magnetic susceptibility of the qubit in the at least one quantum processor, and returning the updated plurality of programmable parameters. Examples programmable parameters include local biases, and coupling values characterizing the problem Hamilton.

Abstract: A higher degree of interactions between qubits is realizable. This disclosure generally relates to devices, and architectures for quantum instruments comprising quantum devices and techniques for operating the same. Systems and processors for creating and using higher degree interactions between qubits may be found herein. Higher order interactions include interactions among three or more qubits. Methods for creating and using higher degree interactions among three or more qubits on a quantum processor may be found herein.

Abstract: Quantum processor based techniques minimize an objective function for example by operating the quantum processor as a sample generator providing low-energy samples from a probability distribution with high probability. The probability distribution is shaped to assign relative probabilities to samples based on their corresponding objective function values until the samples converge on a minimum for the objective function. Problems having a number of variables and/or a connectivity between variables that does not match that of the quantum processor may be solved. Interaction with the quantum processor may be via a digital computer. The digital computer stores a hierarchical stack of software modules to facilitate interacting with the quantum processor via various levels of programming environment, from a machine language level up to an end-use applications level.

Abstract: Systems and devices for providing differential input/output communication with a superconducting device are described. Each differential I/O communication is electrically filtered using a respective tubular filter structure incorporating superconducting lumped element devices and high frequency dissipation by metal powder epoxy. A plurality of such tubular filter structures is arranged in a cryogenic, multi-tiered assembly further including structural/thermalization supports and a device sample holder assembly for securing a device sample, for example a superconducting quantum processor. The ace between the cryogenic tubular assembly and room temperature electronics is achieved using hermetically sealed vacuum feed-through structures designed to receive flexible printed circuit board cable.

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap connector.

Abstract: Fabricating wiring layers above a Josephson junction multi-layer may include removing a part of the multilayer; depositing an insulating layer to overlie a part of the multilayer; and patterning the insulating layer to define a hole in the insulating layer. The method includes depositing a first superconducting wiring layer over a part of the insulating layer and within a portion of the hole. Further, insulating and wiring layers may be deposited and a topmost wiring layer defined. The method includes depositing a passivating layer to overlie the topmost wiring layer. Fabricating a superconducting integrated circuit comprising a hybrid dielectric system may include depositing a high-quality dielectric layer that overlies a superconducting feature. The method includes depositing a second dielectric layer that overlies at least part of the high-quality dielectric layer. The second dielectric layer can comprise a conventional dielectric material.

Abstract: Systems and methods for improving the performance of dilution refrigeration systems are described. Electrostatic cryogenic cold traps employed in the helium circuit of a dilution refrigerator improve the removal efficiency of contaminants from the helium circuit. An ionization source ionizes at least a portion of a refrigerant that includes helium and number of contaminants. The ionized refrigerant passes through an electrostatic cryogenic cold trap that includes a number of surfaces at one or more temperatures along at least a portion of the fluid passage between the cold trap inlet and the cold trap outlet. A high voltage source coupled to the surfaces to causes a first plurality of surfaces to function as electrodes at a first potential and a second plurality of surfaces to function as electrodes at a second potential. As ionized contaminants release their charge on the electrodes, the contaminants bond to the electrodes.

Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.

Abstract: The systems, devices, articles, and methods generally relate to sampling from an available probability distribution. The samples maybe used to create a desirable probability distribution, for instance for use in computing values used in computational techniques including: Importance Sampling and Markov chain Monte Carlo systems. An analog processor may operate as a sample generator, for example by: programming the analog processor with a configuration of the number of programmable parameters for the analog processor, which corresponds to a probability distribution over qubits of the analog processor, evolving the analog processor with a fast ramp operation, and reading out states for the qubits. The state for the qubits may be post processes and/or used to calculate importance weights.

Abstract: Systems and methods for magnetic shielding are described. A magnetic shield formed of a material having a high magnetic permeability may be degaussed using a toroidal degaussing coil. The toroidal degaussing coil may enclose at least a portion of the shield. Magnetic field gradients may be actively compensated using multiple magnetic field sensors and local compensation coils. Trapped fluxons may be removed by an application of Lorentz force wherein an electrical current is passed through a superconducting plane.

Abstract: Systems, methods and aspects, and embodiments thereof relate to unsupervised or semi-supervised features learning using a quantum processor. To achieve unsupervised or semi-supervised features learning, the quantum processor is programmed to achieve Hierarchal Deep Learning (referred to as HDL) over one or more data sets. Systems and methods search for, parse, and detect maximally repeating patterns in one or more data sets or across data or data sets. Embodiments and aspects regard using sparse coding to detect maximally repeating patterns in or across data. Examples of sparse coding include L0 and L1 sparse coding. Some implementations may involve appending, incorporating or attaching labels to dictionary elements, or constituent elements of one or more dictionaries. There may be a logical association between label and the element labeled such that the process of unsupervised or semi-supervised feature learning spans both the elements and the incorporated, attached or appended label.

Abstract: Apparatus and methods enable active compensation for unwanted discrepancies in the superconducting elements of a quantum processor. A qubit may include a primary compound Josephson junction (CJJ) structure, which may include at least a first secondary CJJ structure to enable compensation for Josephson junction asymmetry in the primary CJJ structure. A qubit may include a series LC-circuit coupled in parallel with a first CJJ structure to provide a tunable capacitance. A qubit control system may include means for tuning inductance of a qubit loop, for instance a tunable coupler inductively coupled to the qubit loop and controlled by a programming interface, or a CJJ structure coupled in series with the qubit loop and controlled by a programming interface.

Abstract: Methods and systems represent constraint as an Ising model penalty function and a penalty gap associated therewith, the penalty gap separating a set of feasible solutions to the constraint from a set of infeasible solutions to the constraint; and determines the Ising model penalty function subject to the bounds on the programmable parameters imposed by the hardware limitations of the second processor, where the penalty gap exceeds a predetermined threshold greater than zero. Such may be employed to find quantum binary optimization problems and associated gap values employing a variety of techniques.