Abstract: An approach is described for a method, system, and product, the approaching includes identification of an integrated circuit design, identification of sync groups (nets having synchronous voltage levels), generation of a physical design having sync group constraints, and performance of design rule checking on a physical design based on at least transferred sync group information. This provides for performing design rule analysis at least using small minimum spacing requirements then would otherwise be required with prior techniques. In some embodiments, the approach includes a verification process that ensures that synchronous voltage behavior is appropriately associated with members of respective sync groups and cleans up old association data that is no longer relevant/correct.

Abstract: The present disclosure relates to a method for use in a formal verification of an electronic design. Embodiments may include receiving, using a processor, a reference model including a software specification and an implementation model at a register transfer level. Embodiments may also include generating one or more invariants based upon, at least in part, the reference model, wherein generating one or more invariants includes applying a semantic analysis. Embodiments may further include automatically generating at least one case splitting candidate based upon, at least in part, the one or more generated invariants.

Abstract: The present disclosure relates to a computer-implemented method for use in a formal verification of an electronic design. Embodiments may include receiving a reference model including a software specification, an implementation model at a register transfer level, and a property that analyzes equivalence between the reference model and the implementation model. The method may further include generating one or more case split hints based upon the reference model, that may be used to decompose the design state space into smaller partitions and performing an abstraction operation on a portion of design logic associated with one or more partitions in order to eliminate design elements that are irrelevant to a particular property. Embodiments may also include performing model checking on the abstract models to determine their accuracy.

Abstract: A mid-plane board including a first connector configured to receive a first signal from a first circuit board is provided. The mid-plane board includes a second connector configured to provide the first signal to a second circuit board. The first circuit board forms a first plane and the second circuit board forms a second plane, and the first plane and the second plane are substantially parallel. The mid-plane board also includes a cutout configured to allow a coplanar connector to bridge the mid-plane board and provide a second signal from the first circuit board to the second circuit board. The second signal is a high-end signal and the first signal is a low-end signal, and the mid-plane board is disposed on a plane substantially orthogonal to the first circuit board and the second circuit board.

Abstract: Embodiments disclosed herein describe systems, methods, and products for concurrently placing and optimizing input-output (IO) pins and internal components of an integrated circuit (IC) design. In an illustrative process flow, the computer (executing an illustrative EDA tool) may import the IC design and unplace the IO pins of the imported IC design. The computer may set one or more constraints for the IO pins with more degrees of freedom than the conventional pre-fixed locations. The computer may then concurrently place the IO pins and the internal components such that the IO pins obey the one or more constraints. The computer may iteratively optimize the placement of the IO pins and the internal components while ensuring that the one or more constraints are not violated.

Abstract: The present disclosure relates to a system and method for debugging in fault simulation associated with an electronic design. Embodiments may include receiving, using at least one processor, an electronic design and performing concurrent fault simulation on a fault to be analyzed associated with the electronic circuit design, wherein the fault has a fault propagation path associated therewith. Embodiments may also include identifying a trace of one or more signals of interest that are in the fault propagation path and generating a faulty database and a good database associated with the one or more signals of interest that are in the fault propagation path. Embodiments may further include identifying one or more differences between the faulty database and the good database.

Abstract: Aspects of the present disclosure address improved systems and methods for buffer insertion in an integrated circuit (IC) design using a cost function that accounts for edge spacing and stack via constraints associated with cells in the IC design. An integrated circuit (IC) design comprising a routing topology for a net is accessed. A set of candidate insertion locations along the routing topology are identified. A set of buffering candidates is generated based on the candidate insertion locations. A buffering candidate comprises a cell inserted at a candidate insertion location along the routing topology. A cost associated with the buffering candidate is determined based on a number of potential edge spacing conflicts and a number of stack vias associated with the cell. A buffering solution for the net is selected from the buffering candidate based on the cost associated with the buffering candidate.

Abstract: The present embodiments are generally directed to analyzing clock jitter. Jitter affects the clock delay of the circuit and the time the clock is available at sync points, so it is important to calculate its impact correctly to take appropriate margin during timing analysis. Jitter could be due to various reasons—one of them is due to IR Impact on the Clock Tree. IR drop variations between the two consecutive cycles can effectively reduce the available clock period for data to be correctly captured.

Abstract: Aspects of the present disclosure address systems and methods for fixing clock tree design constraint violations. An initial clock tree is generated. The generating of the initial clock tree comprises routing a clock net using an initial value for a parameter that controls a priority ratio between total route length and a maximum source-to-sink route length in each net of the clock tree. A violation to a clock tree design constraint is detected in the clock net in the clock tree, and based on detecting the violation, a rerouting candidate is generated by rerouting the clock net using an adjusted value for the parameter. A target clock tree is selected based on a comparison of timing characteristics of the rerouting candidate with the clock tree design constraint.

Abstract: Embodiments disclosed herein describe systems, methods, and products for aligning wires in an integrated circuit (IC) design. An illustrative computer may identity multiple references in a first set of wires and multiple targets in a second set of wires in the IC design. The computer may determine reference target pairs from the multiple references and multiple targets. The computer may calculate a path difference for each of the reference target pairs and align the corresponding wires based upon the path difference while obeying minimum spacing rules. The computer may also allow a circuit designer to modify or override the computer selected references, targets, or reference target pairs. Embodiments disclosed herein therefore mitigate the alignment problems of shorting and incorrect spacing.

Abstract: The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using a processor, an electronic design and providing at least a portion of the electronic design to a machine learning engine. Embodiments may further include automatically determining, based upon, at least in part, an output of the machine learning engine whether or not the at least a portion of the electronic design is amenable to formal verification.

Abstract: Embodiments may include receiving an unplaced layout associated with an electronic circuit design and one or more grouping requirements. Embodiments may further include identifying instances that need to be placed at the unplaced layout and areas of the unplaced layout configured to receive the instances. Embodiments may also analyzing one or more instances that need to be placed at the unplaced layout and the one or more areas of the unplaced layout configured to receive the one or more instances. Embodiments may further include determining a location and an orientation for each of the one or more instances based upon, at least in part, the analyzing. Embodiments may also include generating a placed layout based upon, at least in part, the determined location and orientation for each of the one or more instances. Embodiments may further include during the generation of the placed layout, routing the placed layout.

Abstract: The present embodiments relate generally to data communications, and more particularly to systems including high-speed serializer-deserializer circuits having TCOILs. One or more embodiments are directed to a four-terminal TCOIL structure that consumes the same amount of area on a chip as a traditional three-terminal structure, while providing more bandwidth and less reflection and group delay variation.

Abstract: Aspects of the present disclosure address improved systems and methods for rebuffering an integrated circuit (IC) design using a unified improvement scoring algorithm. A plurality of rebuffering candidates are generated based on an initial buffer tree in an integrated circuit (IC) design. A rebuffering candidate in the plurality of rebuffering candidates comprises a modified buffer tree based on the initial buffer tree. A buffering cost of each rebuffering candidate is determined. A reference buffer tree is selected from among the rebuffering candidates based on the buffering cost of each rebuffering candidate. An improvement score of each rebuffering candidate is determined based on the buffering cost of each rebuffering candidate relative to the reference buffer tree. A new buffer tree is selected from among the plurality of rebuffering candidates to replace the initial buffer tree based on the improvement score of each rebuffering candidate.

Abstract: Aspects of the present disclosure address improved systems and methods for runtime efficient circuit placement location selection as described herein. An example embodiment includes identifying, for each route of the one or more routes that interconnect the terminals of a circuit design with the one or more pins of a first circuit element, a corresponding set of movement positions along said each route to generate a set of movement configurations for the first circuit element. The set of movement configurations is analyzed to generate a plurality of location clusters from the set of movement configurations, and for each location cluster of the plurality of location clusters, identifying one or more selected movement configurations within said each cluster. The one or more selected movement configurations for said each cluster to select an updated movement configuration.

Abstract: Various embodiments provide for analyzing (e.g., debugging) waveform data generated for a simulated circuit design, which can be used as part of electronic design automation (EDA). For example, where a user modifies a circuit design in a manner that impacts a next simulation run performed on the circuit design, various embodiments perform the next simulation run only on one or more portions of the circuit design affected by the user's modifications, while the results/simulated values for the rest of the circuit design are kept or reused.

Abstract: Various embodiments provide for generating a routing structure for a clock network based on edge interaction detection, which can facilitate detection/consideration of overuse of routing resources to a balanced routing structure and which may be part of electronic design automation (EDA) of a circuit design. For example, some embodiments use an edge intersection check to detect overuse of routing resources within the routing structure for a clock network.

Abstract: Embodiments described herein provide a new layout editor tool allowing designers to concurrently edit various aspects of an electronic circuit layout, even at disparate hierarchical levels of the design. The new layout editor tool enables multiple electronic circuit designers to concurrently edit a layout a different hierarchical levels, by logically establishing editable child sub cell-level partitions within a parent layout-level partition, each of which representing various components of the same electronic circuit layout.

Abstract: The present embodiments relate to electrostatic discharge (ESD) simulation of integrated circuit designs. A netlist of the circuit design can be modified to include ESD protection devices and only essential non-ESD devices. The essential non-ESD devices can be determined based on whether a non-ESD device satisfies one or more of two conditions: (i) a least resistance path (LRP) value of at least one terminal of the non-ESD device from any port of the set of ports is less than a first threshold value or (ii) an effective resistance value between at least one terminal of the non-ESD device from any port of the set of ports is less than a second threshold value. The essential non-ESD devices are included in a reduced netlist in addition to the ESD protection devices. The ESD simulation is carried out on the reduced netlist, thereby reducing simulation time.

Abstract: The present embodiments relate to static timing analysis (STA) of circuits. The STA can include determining graph based analysis (GBA) delays of timing paths within the circuit. Path based analysis (PBA) delays of a subset of timing paths can be determined to generate circuit stage credit values for circuit stages in the circuit. The circuit stage credit values can be used to adjust GBA delays of the timing paths. Prediction functions can be utilized to predict or estimate PBA delays of timing paths thereby avoiding the determination of actual PBA delays of the timing paths.