Patents Assigned to Design Systems, Inc.
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Patent number: 11270050Abstract: The present disclosure relates to a method for use with an electronic design. Embodiments may include displaying, at a graphical user interface, at least a portion of the electronic design and receiving a selection of a subcircuit at a first position of the graphical user interface. In response to a user input, embodiments may include transitioning the subcircuit from the first position to a second position of the graphical user interface and determining one or more direct and indirect connections resulting from a potential placement at the second position. Embodiments may include determining an influence metric by applying an optimized connectivity rules definition upon the potential placement at the second position and the one or more direct and indirect connections. Embodiments may also include displaying feedback at the graphical user interface based upon, at least in part, the influence metric.Type: GrantFiled: April 16, 2021Date of Patent: March 8, 2022Assignee: Cadence Design Systems, Inc.Inventors: Hitesh Mohan Kumar, Anuj Jain, Sahil Vij, Abhimanyu Bhowmik, Rahul Kumar
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Patent number: 11263381Abstract: Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving, using a processor, an electronic design and providing, at a graphical user interface, an option to change an object associated with the electronic design. Embodiments may further include identifying a damage area associated with the electronic design, the damage area including an object therein. Embodiments may also include generating a polygon for the damage area and caching one or more voids located outside of the damage area. Embodiments may further include performing a cut and stamp operation on a portion of the electronic design associated with the damage area and populating, at the graphical user interface, a repaired damage area.Type: GrantFiled: March 5, 2021Date of Patent: March 1, 2022Assignee: Cadence Design Systems, Inc.Inventors: Randall Scott Lawson, Regis R. Colwell, Richard Allen Woodward, Jr., Rahil Rajesh Kothari, Mahmoodreza Jahanseirroodsari
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Patent number: 11263376Abstract: A computer executable tool fixes gate-level logic simulation when unknowns (Xs) exist in nested clock gater chains to improve simulation accuracy. Due to X-pessimism in logic simulation, false Xs are generated when simulating nested clock gaters, producing incorrect simulation results. The tool analyzes the fan-in cones along a nested clock gater chain to find such false Xs. Furthermore, it generates auxiliary code to be used with logic simulation to eliminate such false Xs. Gate-level simulation can then be repaired to produce correct results for nested clock gaters.Type: GrantFiled: June 23, 2020Date of Patent: March 1, 2022Assignee: Avery Design Systems, Inc.Inventor: Kai-Hui Chang
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Patent number: 11256837Abstract: Disclosed are methods, systems, and articles of manufacture for implementing an electronic design with high-capacity design closure. A reduced netlist may be generated for an analysis view of an electronic design based at least in part upon logic of interest in the analysis view. A closure may be performed based at least in part upon a union netlist, wherein the union netlist is generated from the reduced netlist. The electronic design may then be implemented based at least in part upon a result of the closure task.Type: GrantFiled: June 30, 2020Date of Patent: February 22, 2022Assignee: Cadence Design Systems, Inc.Inventors: Sourav Kumar Sircar, Marc Heyberger, Manish Garg, Akash Khandelwal, Chunlong Pan, Ruchir Agarwal, Anurag Saran, Lalit Bharat, Namrata M Sadhankar, Manish Bhatia, Renuka Deshpande
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Patent number: 11244099Abstract: Aspects of the present disclosure address systems and methods for performing a machine-learning based clustering of dock sinks during clock tree synthesis. An integrated circuit design comprising a clock net that includes a plurality of clock sinks is accessed. A set of clusters are generated by clustering the set of clock objects of the clock net. A machine-learning model is used to assess whether each cluster satisfies one or more design rule constraints. Based on determining each cluster in the set of dusters is assessed by the machine-learning model to satisfy the one or more design rule constraints, a timing analysis is performed to determine whether each cluster in the set of clusters satisfies the target timing constraints. A clustering solution for the clock net is generated based on the set of clusters in response to determining each cluster satisfies the one or more design rule constraints.Type: GrantFiled: December 31, 2020Date of Patent: February 8, 2022Assignee: Cadence Design Systems, Inc.Inventors: Bentian Jiang, Natarajan Viswanathan, Zhuo Li, Yi-Xiao Ding
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Patent number: 11238204Abstract: Various embodiments provide for testing a transmitter with interpolation, which can be used with a circuit for data communications, such as serializer/deserializer (SerDes) communications. In particular, some embodiments provide for data transmission test of a transmitter by: generating and outputting a pre-determined data pattern through a serializer of the transmitter; sampling a serialized data output of the serializer over a plurality of different interpolation phase positions of a phase interpolator; and using a pattern checker to error check the sampled data over the plurality of different interpolation phase positions to determine whether the data transmission test passes.Type: GrantFiled: October 8, 2020Date of Patent: February 1, 2022Assignee: Cadence Design Systems, Inc.Inventors: Scott David Huss, Loren B. Reiss, Fred Staples Stivers, Steven Martin Broome
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Patent number: 11227087Abstract: The present disclosure relates to embodiments for collaborative electronic design. Embodiments may include receiving a baseline model at a computing device associated with each of a plurality of geographically dispersed electronic design teams. Embodiments may further include applying environmental data from each of the plurality of geographically dispersed electronic design teams to the baseline model. Embodiments may also include generating a plurality of training changes, based upon, at least in part, the applied environmental data from each of the plurality of geographically dispersed electronic design teams. Embodiments may also include encrypting the plurality of training changes to create a plurality of encrypted training changes. Embodiments may further include providing the plurality of encrypted training changes to a centralized host configured to aggregate the plurality of encrypted training changes.Type: GrantFiled: January 4, 2019Date of Patent: January 18, 2022Assignee: Cadence Design Systems, Inc.Inventor: David Allan White
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Patent number: 11228416Abstract: Various embodiments provide for calibrating one or more clock signals for a serializer, which can be used with a circuit for data communications, such as serializer/deserializer (SerDes) communications. In particular, for a serializer operating based on a plurality of clock signals, some embodiments provide for calibration of one or more of the plurality of clock signals by adjusting a duty cycle of one or more clock signals, a delay of one or more clock signals, or both.Type: GrantFiled: July 30, 2020Date of Patent: January 18, 2022Assignee: Cadence Design Systems, Inc.Inventors: Scott David Huss, Loren B. Reiss, Christopher George Moscone, James Dennis Vandersand, Jr.
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Patent number: 11188696Abstract: An approach is described for a method, system, and product for deferred merge based method for graph based analysis to reduce pessimism. According to some embodiments, the approach includes receiving design data, static and/or statistical timing analysis data, identifying cells and interconnects for performing graph based worst case timing analysis where merger of signals is deferred based on one or more conditions to reduce pessimism, and generating results thereof. Other additional objects, features, and advantages of the invention are described in the detailed description, figures, and claims.Type: GrantFiled: April 15, 2019Date of Patent: November 30, 2021Assignee: Cadence Design Systems, Inc.Inventors: Amit Dhuria, Sri Harsha Venkata Pothukuchi, Pradeep Yadav, Pawan Kulshreshtha, Igor Keller, Sharad Mehrotra, Jean Pierre Hiol, Krishna Prasad Belkhale
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Patent number: 11188702Abstract: Aspects of the present disclosure address systems and methods for local cluster refinement for integrated circuit (IC) designs using a dynamic weighting scheme. Initial cluster definitions are accessed. The initial cluster definitions define a plurality of clusters where each cluster includes a plurality of pins. Each cluster is evaluated with respect to one or more design rule constraints. Based on the evaluation, clusters are identified from the plurality of clusters. A set of refinement candidates are generated based on the one or more clusters. A scoring function that employs a dynamic weighting scheme is used to determine a refinement quality score for each refinement candidate in the set of candidates and one or more refinement candidates are selected from among the set of refinement candidates based on respective refinement quality scores. A refined clustering solution is generated based on the selected refinement candidates.Type: GrantFiled: December 31, 2020Date of Patent: November 30, 2021Assignee: Cadence Design Systems, Inc.Inventors: Bentian Jiang, Natarajan Viswanathan, William Robert Reece, Zhuo Li
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Patent number: 11190189Abstract: A level shifter circuit comprises a first and second path connected in parallel. The first path comprises three inverters connected in series, and the first path generates a first intermediate clock signal based on an input clock signal. The first intermediate clock signal has a first duty cycle distortion. The second path also comprises three inverters connected in series and the second path generates a second intermediate clock signal based on the input clock signal. The second intermediate clock signal has a second duty cycle distortion. A level shifter output provides an output clock signal based on a combination of the first and second intermediate clock signals. The combination of the first and second intermediate clock signals results in an averaging of the first and second duty cycle distortions in the output clock signal.Type: GrantFiled: August 27, 2020Date of Patent: November 30, 2021Assignee: Cadence Design Systems, Inc.Inventor: Scott David Huss
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Patent number: 11190331Abstract: A physical layer (PHY) device comprises a phase interpolator to generate a set of sampler clocks. A sampler of the PHY device samples a calibration data pattern based on the set of sampler clocks. A data alignment system of the PHY device performs a coarse calibration and a fine calibration on the sampler clock signals. During the coarse calibration, the data alignment system moves the sampler clock signals earlier or later in time relative to the sampled data based on a first bit of the sampled data. During the fine calibration, the data alignment system moves the sampler clock signals earlier or later in time relative to the sampled data based on the first bit, a second bit, and a third bit in the sampled data.Type: GrantFiled: December 16, 2020Date of Patent: November 30, 2021Assignee: Cadence Design Systems, Inc.Inventors: Loren B. Reiss, Scott David Huss, Fred Staples Stivers, James Dennis Vandersand, Jr.
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Patent number: 11184111Abstract: An approach is described for a method, system, and product, the approach includes setting up a sorted unique value array, receiving a user input, receiving data for polar encoding, generating an output array based on locations determined using the sorted unique value array and values determined using the data for polar encoding, and transmit data using 5g wireless communication protocol that has been processed by polar encoding.Type: GrantFiled: September 30, 2019Date of Patent: November 23, 2021Assignee: Cadence Design Systems, Inc.Inventor: Poojan Rajeshbhai Shah
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Patent number: 11165554Abstract: Various embodiments provide for testing a transmitter using a phase-lock loop, which can be used with a circuit for data communications, such as serializer/deserializer (SerDes) communications. In particular, some embodiments provide for data transmission test of a transmitter by: generating and outputting a pre-determined data pattern through a serializer of the transmitter; sampling a serialized data output of the serializer using a sample clock signal generated by an M/N phase-lock loop (PLL); and using a pattern checker to error check the sampled data to determine whether the data transmission test passes.Type: GrantFiled: October 27, 2020Date of Patent: November 2, 2021Assignee: Cadence Design Systems, Inc.Inventors: Scott David Huss, Jeffrey Andrew Shafer
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Patent number: 11163929Abstract: Various embodiments provide for clock network generation for a circuit design using an inverting integrated clock gate (ICG). According to some embodiments, a clock network with one or more inverting ICGs is generated, after a topology of the clock network is defined, by applying a non-inverting ICG-to-inverting ICG transform to one or more nodes of the clock network that comprise a non-inverting ICG. Additionally, according to some embodiments, a clock network is generated bottom-up (from the clock sinks to the root clock signal source) using one or more inverting ICGs.Type: GrantFiled: January 6, 2020Date of Patent: November 2, 2021Assignee: Cadence Design Systems, Inc.Inventors: William Robert Reece, Thomas Andrew Newton, Ruth Patricia Jackson, Zhuo Li
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Patent number: 11165553Abstract: A phase interpolator of a physical layer (PHY) device comprise a phase interpolator to generate a set of asynchronous sampler clocks. A sampler of the PHY device samples a calibration data pattern using a first sampler clock from the set of asynchronous sampler clocks. A calibration control component of the PHY device detects a misalignment of a phase relationship among the set of asynchronous sampler clocks based on the sampled data. In response to detecting the misalignment, the calibration control component calibrates the first sampler clock using a second sampler clock and a third sampler clock.Type: GrantFiled: September 11, 2020Date of Patent: November 2, 2021Assignee: Cadence Design Systems, Inc.Inventors: Loren B. Reiss, Scott David Huss, Christopher George Moscone
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Patent number: 11144698Abstract: An approach is described for a method, system, and product, that includes identification/generation of a synthesized netlist for use in optimization and placement, generation and utilization of multiple uncertainty values for an early clock tree for guiding optimization and placed of circuit elements in a placeopt process that operates on a path by path basis. In some embodiments, the approach further comprises execution of clock tree synthesis, and routing the synthesized clock tree. In some embodiments, uncertainty values are propagated along data paths where each data path is associated with an uncertainty value, and where each path is optimized and placed on a path my path basis in order to meeting timing requirements and one or more design goals.Type: GrantFiled: June 30, 2020Date of Patent: October 12, 2021Assignee: Cadence Design Systems, Inc.Inventors: Vibhor Garg, Edward J. Martinage, Amit Dhuria, Krishna Prasad Belkhale
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Patent number: 11144693Abstract: A method includes generating on a host machine a validated verification test scenario comprising a graph defining a scheduled performance order of a plurality of actions to be performed on a DUT and a corresponding verification environment; obtaining a subset of one or more actions to be added to the validated scenario while maintaining the plurality of actions of the validated scenario and the scheduled performance order, forming an amended verification test scenario; and applying a runtime solver in a target language of the DUT and the corresponding verification environment on the amended verification test scenario to generate a test in a target code and to apply the test on the DUT and the corresponding verification environment wherein inclusion of any of said one or more actions or an order of performance of said one or more actions of the subset in the test is determined at runtime.Type: GrantFiled: November 27, 2019Date of Patent: October 12, 2021Assignee: Cadence Design Systems, Inc.Inventor: Meir Ovadia
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Patent number: 11132489Abstract: Various embodiments provide for layer assignment of a network of a circuit design based on a wirelength threshold, which can facilitate consideration of timing and electromigration and which may be part of electronic design automation (EDA) of a circuit design. More particularly, some embodiments determine (e.g., calculate) a wirelength threshold for a net (e.g., each net) of a circuit design based on one or more characteristics of the net, and select a layer for at least a portion of the net based on the wirelength threshold.Type: GrantFiled: February 28, 2020Date of Patent: September 28, 2021Assignee: Cadence Design Systems, Inc.Inventors: Derong Liu, Yi-Xiao Ding, Zhuo Li, Mehmet Can Yildiz
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Patent number: 11133793Abstract: Various embodiments provide for phase interpolators with phase adjusters to provide step resolution, which can be used with a circuit such as a data serializer/deserializer circuit. In particular, for some embodiments, a phase interpolator is coupled to a phase adjuster, where the combination of the phase interpolator and the phase adjuster is configured to interpolate between phases in phase adjustment steps at a phase adjustment step resolution. For such embodiments, the phase adjustment step resolution of the steps is achieved by controlling the phase interpolator and the phase adjuster.Type: GrantFiled: December 1, 2020Date of Patent: September 28, 2021Assignee: Cadence Design Systems, Inc.Inventors: Scott David Huss, Loren B. Reiss, Christopher George Moscone, Kelvin E. McCollough