Patents Assigned to Design Systems, Inc.
  • Patent number: 11132490
    Abstract: Various embodiments provide for clock network generation for a circuit design using a negative-edge integrated clock gate (ICG). According to some embodiments, a clock network with one or more negative-edge ICGs is generated, after a topology of the clock network is defined, by applying a positive-edge ICG-to-negative-edge ICG transform to one or more nodes of the clock network that comprise a positive-edge ICG. Additionally, according to some embodiments, a clock network is generated bottom-up (from the clock sinks to the root clock signal source) using one or more negative-edge ICGs.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: September 28, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ruth Patricia Jackson, William Robert Reece, Thomas Andrew Newton, Zhuo Li
  • Patent number: 11132619
    Abstract: Some embodiments perform, in a multi-layer neural network in a computing device, a convolution operation on input feature maps with multiple convolutional filters. The convolutional filters have multiple filter precisions. In other embodiments, electronic design automation (EDA) systems, methods, and computer-readable media are presented for adding such a multi-layer neural network into an integrated circuit (IC) design.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: September 28, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Raúl Alejandro Casas, Samer Lutfi Hijazi, Piyush Kaul, Rishi Kumar, Xuehong Mao, Christopher Rowen
  • Patent number: 11128410
    Abstract: Embodiments disclosed are directed to methods for scheduling packets. According to example embodiments the method includes receiving, using a first layer in a communication protocol, a first request from a second layer in the communication protocol. The first request indicates to the first layer to output a data stream that includes a first location for the second layer to include a first control packet. The first layer is at a higher level of abstraction than the second layer. The method further includes transmitting, using the first layer, a first response to the second layer. The first response is based on the first request, and the first response identifies the first location in the data stream and a time of occurrence of the first location in the data stream.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: September 21, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Chetan Paragaonkar, Gopi Krishnamurthy, Anish Mathew, Raveendra Pai Gopalakrishna, Anujan Varma
  • Patent number: 11108425
    Abstract: A calibration control component within a transmit (TX) or receive (RX) device executes a calibration sequence to ensure reliable data transmission and reception within the device. The calibration sequence comprises a set of calibration functions that are sequentially executed. The calibration control component detects a pause function being enabled based on a pause function configuration register. Based on detecting the pause function being enabled, the calibration control component pauses execution of the calibration sequence.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: August 31, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Scott David Huss, Loren B. Reiss, Fred Staples Stivers, Matthew Robert Collin, James Lee House, Ramakrishna Kasukurthi
  • Patent number: 11100268
    Abstract: Embodiments are generally directed to a hierarchical approach for performing simulation for PDNs that have integrated VRMs. According to certain aspects, embodiments include an approach that decouples the simulation for PDN and the simulation for VRM/PKG through PDN macromodeling. In these and other embodiments, the approach includes a SPICE-accurate simulation for the VRM part using a non-linear solver and using a linear solver for the PDN part, with minimal handshaking between them. For example, using a Backward Euler method having a fixed time step, at every simulation time interval, the linear solver sends reduced boundary currents to the non-linear solver. After the non-linear solver converges at the time interval, it sends boundary voltages back to the linear solver for determining voltages in the PDN part at the time interval.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: August 24, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Zhiyu Zeng, Hailin Jiang, Yanfei Gu, Nityanand Rai, Xin Gu
  • Patent number: 11087064
    Abstract: The present disclosure relates to a method for use with an electronic design. Embodiments may include receiving, using a processor, the electronic design and estimating a wire width associated with the electronic design based upon, at least in part, a current in a wire, a layer of the wire, a temperature, and an electromigration length. Embodiments may further include allowing, at a graphical user interface, a user to make an edit to a shape or a layer of the wire and generating a revised EM length, based upon, at least in part, the edit. Embodiments may also include generating one or more EM length breakpoints based upon, at least in part, the revised EM length and one or more EM rules.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: August 10, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Laurent René Saint-Marcel, Olivier Berger
  • Patent number: 11087060
    Abstract: The present disclosure relates to a computer-implemented method for electronic design. Embodiments may include receiving, using at least one processor, an electronic design schematic and an electronic design layout and training a model using at least one predictor associated with the electronic design layout. Embodiments may further include obtaining an updated model, based upon, at least in part, the training. Embodiments may also include applying the updated model to a second electronic design schematic or a second electronic design layout, wherein one or more hard constraints or one or more soft constraints or both are created, based upon, at least in part, the model.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: August 10, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Wangyang Zhang, Elias Lee Fallon, Regis R. Colwell, Hua Luo, Namita Bhushan Rane, Sheng Qian
  • Patent number: 11080448
    Abstract: A method for formal deep bug hunting in a device under test (DUT) may include obtaining a selection of a start state for the DUT; obtaining a selection of one or a plurality of variables that are declared as random variables; for each of said one or a plurality of random variables, generating a sequence of random values in a generation order using a random number generator (RNG); and performing formal verification exploration of the DUT starting at the start state and consecutively assigning each of said one or a plurality of random variables a value from the sequence of values in the generation order.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: August 3, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yaron Schiller, Guy Wolfovitz, Habeeb Farah
  • Patent number: 11080444
    Abstract: Devices, methods, computer-readable media, and other embodiments are described for concurrent functional and fault co-simulation of a circuit design. One embodiment involves accessing simulation data for a circuit design made up of a plurality of machine regions. A plurality of faults is selected from the simulation data for co-simulation operations of functional simulation and fault simulation of the circuit design, and functional simulation of the plurality of machine regions is initiated using the simulation data. A first machine region is identified during the functional simulation as associated with at least a first fault of the plurality of faults. A functional simulation of the first machine region is performed, and a divergence point associated with the first fault is identified. A fault simulation for the first fault is performed using the functional simulation of the first machine region and the divergence point.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: August 3, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Manoj Kumar, David J. Roberts, Apurva Kalia
  • Patent number: 11080457
    Abstract: Various embodiments provide for layer assignment of a network of a circuit design based on a resistance or capacitance characteristic, such as a resistance/capacitance characteristic associated with a layer, a wire, or a via of the circuit design. In particular, various embodiments consider a resistance/capacitance characteristic of a layer, a wire, or a via of a circuit design to determine a set of layers for routing one or more networks of the circuit design, which can enable some embodiments to route the networks on the layers within a certain range that has very close resistance/capacitance (RC) characteristics, and can permit routing each network on layers having the smallest RC characteristic difference.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: August 3, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Derong Liu, Yi-Xiao Ding, Mehmet Can Yildiz, Zhuo Li
  • Patent number: 11048852
    Abstract: The present disclosure relates to a computer-implemented method for electronic circuit design. Embodiments may include receiving, using at least one processor, data corresponding to an electronic design schematic. Embodiments may further include analyzing the data to learn one or more device size parameters, a range of parameters, or a matching relationship of parameters based upon, at least in part, the electronic design schematic or the electronic design layout, wherein analyzing occurs without user action.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: June 29, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Elias Lee Fallon, Wangyang Zhang, Sheng Qian
  • Patent number: 11048843
    Abstract: A compaction circuit in an emulation system may store in a data array emulation data that may be read in subsequent emulation steps. For each emulation step, the compaction circuit may receive keeptags from a local control store word of the emulation step and store portions of emulation data identified by the keeptags. The keeptags in the control store words may be inserted by a compiler based upon whether a corresponding read port of emulation processor reads the stored data in the subsequent steps. The compaction circuit may also translate the logical read address of the stored data to a physical read address in the shared data array. A dynamic modification engine may enable dynamic modification of netlists while using the compacted data array. In response to a request, the dynamic modification engine may modify one or more keeptags and update read addresses in the control store words.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: June 29, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Mitchell G. Poplack, Yuhei Hayashi
  • Patent number: 11042684
    Abstract: Embodiments according to the present disclosure relate to physically implementing an integrated circuit design using track patterns while conforming to the requirements of complex color based track systems, and using information about instances that have been included in the design. According to some aspects, the present embodiments provide “Dynamic Width Space Patterns (DWSP)” which are WSPs that are modified dynamically in consideration of neighboring geometries such that shapes created or edited using WSPs are design rule compliant. Embodiments can include providing visual indicators in a display of a portion of a design that is being created or edited, as well as possibly other alerts, so as assist a designer in creating a design rule compliant integrated circuit design that is also subject to WSPs.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: June 22, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventor: Sachin Srivastava
  • Patent number: 11042500
    Abstract: A SPI master may configure a set of hardware registers associated with a SPI client with a set of communication parameters. The SPI master may send a message to the SPI client. The SPI master may periodically ping the SPI client until the SPI master receives an acknowledgement message from the SPI client in response to the message from the SPI master. The SPI master may periodically ping the SPI client based upon the set of communication parameters. The SPI client may transmit the acknowledgement message to the SPI master based upon the set of communication parameters. The SPI master may receive the acknowledgement message from the SPI client. The SPI master may determine a status of a read operation or a write operation associated with the message based upon the acknowledgement message.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: June 22, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Xiaolei Guo, Mitchell Poplack
  • Patent number: 11041316
    Abstract: Disclosed is a section of wall cladding comprises of a panel comprising a front side and a back side, a front hem at a top of the panel formed from a portion of material turned toward the front side of the panel and downward, and a rear hem at a bottom of the panel formed from a portion of material turned toward the back side of the panel and upward. The section of wall cladding can be t-shaped or any other shape to depending on the desired aesthetics.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: June 22, 2021
    Assignee: Metal Design Systems, Inc.
    Inventor: David A. Sauerwein
  • Patent number: 11030378
    Abstract: Various embodiments described herein provide for track assignment of wires of a network of a circuit design by dynamic programming. In particular, various embodiments use a dynamic programming process to determine a set of breaking points for a routing wire of a global-routed and layer-assigned circuit design, and to determine track assignments for each of the sub-wires (sub-routes) formed by applying the set of selected breaking points to the routing wire. This results in a set of track-assigned sub-wires (or track-assigned sub-routes), which various embodiments can connect together to generate a connected set of track-assigned sub-wires that can be used in place of the routing wire.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: June 8, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yi-Xiao Ding, Mehmet Can Yildiz, Zhuo Li
  • Patent number: 11030377
    Abstract: Various embodiments described herein provide for routing of wires of a network of a circuit design based on pin placement within a routing blockage. In particular, various embodiments provide a routing solution for a circuit design with zero blockage violation when there is no pin inside routing blockage of the circuit design, and uses a parameter (e.g., an adjustable parameter) that controls accuracy at which a routing process handles a pin (e.g., as placed by a placement stage) in routing blockage of the circuit design. For example, the parameter can control how much detour is acceptable when handling routing for a pin inside a routing blockage.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: June 8, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Wing-Kai Chow, Mehmet Can Yildiz
  • Patent number: 11023640
    Abstract: Disclosed are methods, systems, and articles of manufacture for characterizing timing behavior of an electronic design with a derived current waveform. A set of inputs is determined from a set of electrical characteristics of an electronic design or a portion thereof. Moreover, A derived current waveform is determined at one or more modules stored in memory and executing in conjunction with a microprocessor of a computing node based at least in part upon the set of inputs. The electronic design or the portion thereof is characterized based at least in part upon the derived current waveform.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: June 1, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Igor Keller, Chirayu S. Amin, Omid Assare
  • Patent number: 11023357
    Abstract: A method for sequential equivalence checking (SEC) of two representations of an electronic design may include using a processor, automatically selecting a plurality of cutpoints in the two representations of the electronic design; using a processor, automatically executing a prove-from strategy on the plurality of cut point pairs to identify a failed cut point pair in the two electronic designs; and using the processor, automatically extending a trace corresponding to the identified failed cut point pair to identify a deeper failed cut point pair or a failed output pair in the two electronic designs.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: June 1, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ayman Hanna, Karam Abdelkader, Doron Bustan, Habeeb Farah, Thiago Radicchi Roque, Felipe Althoff
  • Patent number: 11023636
    Abstract: Disclosed are methods, systems, and articles of manufacture for characterizing an electronic design with a susceptibility window. These techniques identify a set of multiple aggressors in an electronic design and determine, at a susceptibility window module stored in memory and executing in conjunction with a microprocessor of a computing node, a susceptibility window for an internal node of a victim and a timing window for the set of multiple aggressors in the electronic design. These techniques further determine a subset having at least one aggressor using at least the susceptibility window of the victim and the timing window for the set of multiple aggressors, and determine whether a glitch in the electronic design causes a violation at the internal node of the electronic design based at least in part upon the timing window and the susceptibility.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: June 1, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Igor Keller, Ratnakar Goyal, Manuj Verma, Harmandeep Singh