Abstract: A method for performing multiple simulations for a circuit using a first plurality of samples is provided. The method includes obtaining a model of the circuit based on a result of the simulations, determining a failure rate and a confidence interval of the failure rate for the circuit with the performance model. The method includes determining an importance distribution based on the failure rate for the first plurality of samples, wherein the importance distribution is indicative of a probability that a sample value for the circuit will fail the simulation, selecting a second plurality of samples based on the importance distribution, performing a second set of simulations using the second plurality of samples to reduce the confidence interval of the failure rate. When the confidence interval is larger than a value, obtaining an updated performance model and performing new Monte Carlo simulations with new samples.

Abstract: A method for receiving a circuit layout including modules in a hierarchical structure. The method includes selecting a module in the hierarchical structure, identifying multiple toggling netlists in the module during multiple clock cycles, grouping the toggling netlists into clusters based on a toggle weight factor, and finding an average toggle weight factor for each cluster. The method includes generating instrument logic to determine a power consumption of the circuit layout based on a number of toggling netlists in each cluster for each clock cycle, and on the average toggle weight factor for each cluster, merging, with a compiler tool, the instrument logic with the circuit layout into an executable file for an emulator tool. The method includes evaluating the power consumption of the circuit layout with the emulator tool; and modifying the circuit layout when the power consumption of the circuit layout exceeds a pre-selected threshold.

Abstract: Disclosed are methods, systems, and articles of manufacture for characterizing electronic designs with electronic design simplification techniques. These techniques identify an input for simplifying an electronic design and generates a simplified electronic design at least by performing layout simplification on the electronic design. A characterization input may be determined for subsequent characterization of the simplified electronic design. An electromagnetic behavior of the simplified electronic design may then be characterized using at least the characterization input.

Abstract: An approach is described for determining waiver applicability conditions and applying the conditions to multiple errors or warnings in physical verification tools. According to some embodiments, the approach includes identification of a waiver of an error or warning, registration of one or more condition sets for waiver of an error or warning, waiver of multiple errors or warnings that match the registered one or more condition sets, and further comprise any or all of the following: receiving or retrieving a circuit design, analyzing the circuit design to identify errors and warnings, and displaying identified errors and warnings where errors and warnings matching a registered condition set are waived. This approach provides for a 1-to-many relationship between identification of a waiver and application of waivers.

Abstract: A reconfigurable switching apparatus may include a plurality of communications transceivers operable to connect to a plurality of programmable integrated circuits. The reconfigurable switching apparatus may further include a plurality of crosspoint switches operably coupled to the plurality of communications transceivers. The reconfigurable switching apparatus may further include a processing circuitry operably coupled to the plurality of crosspoint switches and operable to program the plurality of crosspoint switches to route a plurality of interconnection paths between the plurality of communications transceivers.

Abstract: Various embodiments provide for modeling a power and ground (PG) mesh for a circuit design placement process. For some embodiments, a reference PG mesh can be used to generate a PG mesh model for a circuit design. A PG mesh model can be generated for a circuit design by calculating how much routing resource is occupied by the reference PG mesh of the circuit design, and the resulting PG mesh model can be applied to the circuit design by removing a similar amount of routing resource from the circuit design during a placement circuit design flow. Additionally (or alternatively), a PG mesh model can be generated to comprise a set of metal obstructions that correspond to each macro of the circuit design, and the PG mesh model can be applied to the circuit design by adding the metal obstructions to one or more metal layers of the circuit design.

Abstract: An approach is described for a method, system, and product for generating radial bump patterns. According to some embodiments, the approach includes determining parameters for radial pattern generation in a precomputing phase, creating a radial pattern in a second stage, and generating a layout from the radial pattern in the second stage before manufacture a device embodying the radial pattern. In some embodiments, the radial pattern comprises rings having a number of rows where bump instances are placed and rotated such that they are perpendicular to a radius from a common center line. Furthermore, in some embodiments, the number of rows in a ring is generated pursuant to a set value or dynamically generate based on one or more optimization metrics.

Abstract: Aspects of the present disclosure address systems and methods for functional coverage in integrated circuit (IC) designs utilizing arbitrary expression to define irrelevant domains in coverage item definitions. A coverage item definition is determined to include an arbitrary expression that defines an irrelevant domain for a coverage item in a functional coverage analysis of an IC design. Based on determining if the item definition comprises the arbitrary expression, a verification the arbitrary expression satisfies one or more analyzability conditions is performed. Based on verifying the arbitrary expression satisfies the one or more analyzability conditions, the irrelevant domain for the coverage item is calculated based on the arbitrary expression. An enhanced functional coverage model that excludes the irrelevant domain for the coverage item is generated and used to perform the functional coverage analysis on the IC design.

Abstract: A method for emulating an image processing system on an emulator may include pre-processing of image files that comprises converting each of the image files to a file of low-level image data packets; when emulating the image processing system on the emulator, loading each of the files of low-level image data packets to a memory of the emulator; reading the loaded file from the memory and streaming that file of said files of low-level image data packets to the emulated image processing system.

Abstract: Various embodiments provide for routing a network of a circuit design based on at least one of via spacing or pin density. For instance, some embodiments route a net of a circuit design (e.g., data nets, clock nets) by generating a congestion map based on modeling via spacing, modeling pin density, or some combination of both.

Abstract: Electronic design automation systems, methods, and media are presented for clock gate placement with data path awareness. One embodiment involves accessing a circuit design with a clock tree, clock gates, and an initial movement area. A set of positions for a set of data path connection points associated with the data routing lines are identified, along with an expansion direction from the initial placement position toward the set of positions for the set of data path connection points, and the initial movement is expanded to consider additional placement options for the clock gate based on the data path connection points.

Abstract: Various embodiments described herein provide for a data transfer mechanism for a memory device, such as a Double Data Rate (DDR) memory device, which can improve critical timing within the memory device without a latency impact. In addition, various embodiments described herein provide for a switching sequence for a memory device, which can improve switching time for the memory device.

Abstract: An approach is described for a method and apparatus for a low energy programmable vector processing unit for use in processing such as for example neural network backend processing. According to some embodiments, this approach provides a pooling/vector processing unit for performing backend processing that implements a single issue multiple data (SIMD) datapath that performs various backend processing functions using only a single instruction. For instance, the present approach provides an apparatus and method for execution of operations in parallel using a single issued instruction to a plurality of processing cells. In some embodiments, there are multiple groups of processing cells for performing different operations—e.g. pooling, permute, sigmoid/tanh, and element wise operations.

Abstract: Disclosed are methods, systems, and articles of manufacture for probing a multi-fabric electronic design that spans across multiple design fabrics. These techniques identify a single layout editor, a first electronic design in a first design fabric, and a second electronic design in a second design fabric. An input for probing a circuit component in the first electronic design may further be identified at a user interface of a computing system. The circuit component being probed is connected to an instance of the second electronic design. In response to the input, one or more co-design modules render a representation of the first layout with emphasized circuit components in the first design fabric and the second design fabric, wherein the one or more co-design modules are stored at least partially in memory of and function in conjunction with at least one microprocessor of a computing system.

Abstract: According to certain aspects, the present embodiments are directed generally to data communication systems, and more particularly to generating multi-phase clocks in a SerDes system. Embodiments provide SerDes components and methods that are capable of generating multiple different sampling frequencies for parallelizing serial data from a single high speed clock. These and other embodiments can be implemented with circuits that are relatively small and low-power as compared to conventional approaches.

Abstract: Disclosed are methods, systems, and articles of manufacture for reducing interferences and disturbances in a multi-fabric electronic design. These techniques identify connectivity for an electronic design that includes design data in multiple design fabrics. One or more interference modules are executed to detect a loop in the electronic design with at least the connectivity. These techniques further execute the one or more interference reduction modules to determine at least one critical circuit component upon which the loop exerts a negative impact. One or more remedial actions are then triggered to reduce or eliminate the negative impact on the critical circuit component design.

Abstract: Aspects of the present disclosure address a slew rate controlled driver. The slew rate controlled driver includes an amplifier with a capacitive feedback loop and a current generator capable of producing a current that is proportional to on-chip capacitance. The current generator is implemented using a switched capacitor and supplies the driver with a current that is proportional to the capacitance of the switched capacitor. By supplying the driver with current that is proportional to the capacitance of the switched capacitor, the slope of the output signal of the driver is proportional to the ratio of the switched capacitance and a capacitance of the driver's capacitive feedback loop.

Abstract: Aspects of the present disclosure address improved systems and methods for layer assignment to improve timing in integrated circuit (IC) designs. An initial placement layout of a net of an IC design is accessed. A plurality of buffer insertion candidates is generated using multiple candidate buffer insertion points and multiple layer assignments from among multiple layers of the IC design. Timing characteristics of each buffer insertion candidate are determined, and timing improvements provided by each buffer insertion candidate are determined based on respective timing characteristics. A buffer insertion candidate is selected from the plurality of buffer insertion candidates based on the timing improvement provided by the buffer insertion candidate. A layout instance for the IC is generated based in part on the selected buffer insertion candidate.

Abstract: Disclosed herein are systems and methods of compiling resources of a programmable emulation system to execute an emulation process, to emulate a logic system, such as an application-specific integrated circuit (ASIC), currently being tested and prototyped, and then revising, transforming, and moving the compiled instructions sets to inexpensively, quickly, and dynamically adapt to unavailable resources, which may be due to previously allocation to a different emulation job, or for fault tolerance. Relocation of the resources that will execute the emulation job (i.e., “footprint”) may refer to the remapping of a compiled footprint to a revised set of resources, defining a revised footprint. Fault tolerance may refer to support for working around faulty hardware components of the emulation system.

Abstract: Various embodiments provide for assigning a clock pin to a clock tap within a circuit design based on connectivity between circuit devices of the circuit design. For some embodiments, an initial clock tap assignment, between a clock tap of a circuit design and a clock pin of the circuit design, is accessed as input, and a modified clock tap assignment (between the clock tap and another clock pin of the circuit design) can be generated based on one or more of the following considerations: a clock tap assignment should try to assign clock pins of connected circuit devices to the same clock tap; a clock tap assignment should try to assign clock pins of connected circuit devices having the critical timing problems; a clock tap assignment should try to assign clock pins of connected circuit devices to clock taps with longer common path length.