Abstract: A circuit and method is described for automatically testing multiple LDO regulator circuits on an integrated circuit chip independent of an ATE. Each LDO regulator is tested for voltage at a specified current output capability, wherein the output driver transistor is formed by at least two pass transistors, which are each tested for voltage output at a particular current capability. The test results are delivered back to the ATE and for a failed test, the gate voltage of the pass device can be observed through an analog multiplexer to enable debug.

Abstract: Circuits and methods to compensate leakage current of a LDO are disclosed.

Abstract: Systems and methods for providing a fully differential amplifier performing common-mode voltage control having reduced area and power requirements are disclosed. The amplifier disclosed comprises an additional input stage at the amplifier input which senses the common mode voltage of the amplifier's inputs and applies internal feedback control to adjust the output common-mode voltage until the input common-mode voltage matches a target voltage and thereby indirectly set the output common-mode voltage. Furthermore the internal common-mode control can be implemented in such a manner as to provide a feed-forward transconductance function in addition to common-mode control if desired. Moreover it is possible to use feedback from other amplifier stages in an amplifier chain to implement common-mode feedback.

Abstract: Circuits and methods to achieve a new fully differential amplifier topology in class AB mode are disclosed. In a preferred embodiment of the disclosure the differential amplifier is diving dynamic speakers. An differential intermediate stage combines four different feedbacks, all sharing four high impedance nodes: main loop regulation feedback, common mode regulation feedback, and output stage quiescent current regulation for both differential output stage branches.

Abstract: The present document relates to providing power for driving SSL devices. A power converter converts a varying input voltage to supply an output voltage to a SSL device in series with a current source. The power converter comprises one or more capacitors; a plurality of switches to couple the capacitors in a plurality of configurations. A control unit operates the power converter in a plurality of operational modes providing a corresponding plurality of different conversion ratios between the input/output voltages. The operational modes comprise a first phase and a second phase, during which the capacitors are differently arranged. The control unit controls the switches to alternate between the phases at a commutation cycle rate. The control unit sets the operational mode based on the varying input voltage.

Abstract: Circuits and methods to achieve a most efficient driver for white LEDs are disclosed. Switching Losses associated with the switching activity of a boost converter and mainly depending on clock frequency and total capacitance at the switching nodes and conduction losses associated with the current flowing in the boost converter and mainly depending on the series resistance of the elements in the regulation loop are minimized by using a size programmable NFET power switch with constant current limit, a very low voltage and accurate programmable current source, a programmable reference voltage for the error amplifier, and a PWM generator with programmable clock frequency. A limited number of configuration windows corresponding to a set of programmable values (OTP registers) for specific ranges of the current fed to the WLEDs.

Abstract: Described is a rectification circuit to generate a direct current at an output of the rectification circuit subject to an alternating voltage at an input of the rectification circuit. The rectification circuit comprises: coupling means at the input to receive the alternating voltage from a galvanically decoupled electronic subsystem; a first switch arranged between the coupling means and the output to block current in a first direction and to conduct current in a second direction, wherein a resistance of the first switch is adjustable; a first modulation unit to receive encoded information; mapping the encoded information to a first modulation state, wherein each modulation state specifies a resistance value and/or a temporal evolution of the resistance value; adjusting the resistance of the first switch, thereby modulating the current conducted by the first switch according to the first modulation state.

Abstract: Disclosed are systems and methods to achieve a low noise, fully differential amplifier with controlled common mode voltages at each stage output but without the requirement of a common mode feedback loop. Common mode voltages are adjusted by adjusting the currents flowing through the load impedances (bias currents) wherein the currents are derived from one or more voltage-to-current converters based on an impedance that matches to the load impedances of the stages of the amplifier. The amplifier invented is primarily used for amplification of low frequency signals. The amplifier has one or more gain stages applying only one conduction type of transistors of an IC technology that has the lowest transition frequency between 1/f noise and white noise to achieve a low chopping or autozeroing frequency.

Abstract: This disclosure relates to illumination systems. In particular it relates to a method and system for avoiding flicker (in particular 100 Hz or 120 Hz flicker) in solid state lighting devices such as LED or OLED assemblies. A controller for a driver circuit of a solid state lighting device (SSL) is described. The driver circuit comprises a power converter to convert a varying input voltage into a drive voltage for the SSL device. The input voltage is derived from a rectified AC mains voltage and frequency. The power converter is used with a maximum voltage step-up conversion ratio. The controller synchronizes to the mains frequency and determines a plurality of pulse intervals repeated at a pulse frequency where the pulse frequency is greater than a perceptual frequency of light intensity variations perceivable by a human eye.

Abstract: Circuits and methods for fast detection of a low voltage in the range of few ?Volts have been achieved. In a preferred embodiment the low voltage represents a current via a shunt resistor and the circuit is used to generate a digital wake-up signal. In regard of the wake-up application the circuit invented is activated periodically and in case of a certain level of the voltage drop, e.g. 50 ?V, at the shunt resistor. The time required for a measurement of the voltage drop is inclusive calibration and integration time far below 1 ms. It is obvious that the circuit invented can be used for any measurements of very small voltages.

Abstract: Systems and methods to achieve a charge pump for generating from a single input supply voltage Vdd in three modes efficient output supply voltages having a value of 2×Vdd, ½ Vdd, and inverted Vdd. The charge pump requires 8 switches and one flying capacitor only.

Abstract: The present disclosure provides circuitry and a method for digital clock generation including the generation of integer and non-integer sub clocks. The proposed method provides simplified constant signal propagation and low skew in the divided clock path independent of division factor. Also provided is a simplified mechanism for generating low power clock patterns divided down by factors which are non-integer, phase-shifted, repeated pulse trains, dynamically changing and glitch-free.

Abstract: The present document relates to a method and system for determining the voltage level of an input signal compared to a reference voltage, providing a plurality of level indications regarding an input voltage with respect to a reference voltage. The multi-level comparator comprises an input stage converting the input voltage into a first current and converting the reference voltage into a second current; and a plurality of comparator stages, each comprising a first current amplification unit amplifying the first current with a first gain, a second current amplification unit amplifying the second current with a second gain, and an output port providing an indication whether the first comparator current is smaller or larger than the second comparator current; wherein respective ratios of the first gain and the second gain of the plurality of comparator stages are different.

Abstract: Circuits and methods for a switched power converter providing charge power for at least one battery and at the same time delivering current to operate an electronic device, wherein the converter is enabled to operate out of current limit mode, for the maximum possible range of system load requirements, have been achieved. The input current of the power converter is measured within each cycle-by-cycle, i.e. within each cycle of an external clock reference and the charge current is reduced if the input current exceeds a defined portion, e.g. 80% of the maximum allowable input current. The power converter may only enter current limited operation after the charge current has been already reduced to zero. Operating out of current limit mode ensures a maximum efficiency of the converter, maximize the current deliverable to a given load and minimizes subharmonics in the output current and voltage, thereby minimizing interference with other system component.

Abstract: The LDO has at least three stages supplied by a supply voltage. A first stage has a differential amplifier and a folded cascode device with a regulated current mirror. The LDO has two nodes that are configured to couple the differential amplifier and the regulated current mirror and to receive a differential signal, respectively. The regulated current mirror is configured to convert and amplify the differential signals to a single ended signal. Said LDO has a first capacitor configured for frequency compensation, said first capacitor coupled between said first stage and a second stage. The LDO has a second capacitor for balancing capacitive loading of a first cascode circuit, said second capacitor coupled between said first stage and said supply voltage. Said first cascode circuit is configured to suppress different voltages between input and output of the capacitors caused of a modulation of said supply voltage.

Abstract: A method and circuits to limit the output load current of a current driven LDO voltage regulator are disclosed. The current through a second pass transistor, being in parallel to a first pass transistor and being a fraction of the current through the first pass transistor is measured and compared with a reference current. In case the current through the second pass transistor is larger than this reference current the current through the gates of both pass devices is reduced and thus the output load current of the voltage regulator is limited.

Abstract: The present document relates to power converters. In particular, the present document relates to a scheme for operating a low side switch of a power converter in the safe operation area. A power converter converting an input voltage to an output voltage is described. The power converter comprises a low side switch configured to couple an inductor to ground during an on-state of the low side switch; wherein the inductor is configured to store energy to be provided to a load at the output of the power converter; and a protection switch in parallel to the low side switch, configured to reduce a voltage drop across the low side switch during at least part of a switch off time of the low side switch.

Abstract: The present document relates to the control of an external power transistor. In particular, the present document relates to a method and system for avoiding ringing at the external power transistor subsequent to switching of the external power transistor. A driver circuit to generate a drive signal for switching a driven switch between an off-state and an on-state is described. The driver circuit comprises a drive signal generation unit configured to generate a high drive signal triggering the driven switch to switch to the on-state; wherein an output resistance of the driver circuit is adjustable; an oscillation detection unit to detect a degree of oscillation on the drive signal; and a resistance control unit to adjust the output resistance of the driver circuit based on the degree of oscillation on the drive signal.

Abstract: The present document relates to switched power supplies. In particular, the present document relates to a method and system for controlling a bypass transistor in a DC-to-DC converter. A power converter configured to convert an input voltage at an input of the power converter into an output voltage at an output of the power converter is described. The power converter comprises a DC-to-DC converter comprising a high side switch; a bypass transistor parallel to the DC-to-DC converter, configured to couple a load at the output of the power converter to the input voltage during an on-state of the bypass transistor; and current sensing means configured to sense a current through the high side switch; wherein the bypass transistor is controlled based at least on the sensed current through the high side switch.

Abstract: Circuits and methods to limit an in-rush current of a load circuit such as a processor are disclosed. A charge pump is used as driver for switches with pulse modulation width (PWM) control on the duty cycle of a clock. A clock generator generates a ramp signal with variable slope and a reference voltage. The slope of the ramp signal is dependent on the in-rush current of the switch. No dedicated slew rate driver or an external capacitor is required. The main building blocks are: a charge pump used as driver connected to single supply domain, one external (or internal) switch device, a single capacitive feedback between the switch device and the PWM control, and a PWM control comprising a fix frequency voltage triangular pulse generator with variable slope proportional to the in-rush current measurement.