Abstract: A circuit and a method are provided for suppressing the pop and click noise during the power on and power off of Class D amplifiers. The technique also suppresses pops and clicks when the Class D amplifier enters or exits standby mode. A duplicate feedback network is used to establish the stable operating points, including offsets in the Class D circuit without turning on the outputs. The technique works by gradually propagating or dissipating the offset through the signal path of a Class D amplifier by swapping the differential outputs using switches to suppress pops and clicks when starting up and shutting down the amplifier.

Abstract: A circuit and methods eliminating production related luminance variations of electronic display applies to all display technologies that require gamma adjustment or also adjustment of other display parameters e.g. brightness or contrast as e.g. LCD or OLED display modules are disclosed. This is performed by individual trimming of the display driver's gamma curve One alternative is that an end-user has access to a non-volatile memory and replaces the factory default settings of the gamma curve with individual settings. Another alternative is to load gamma curve parameters from the non-volatile memory to gamma control registers and perform tweaking of the gamma curve from these control registers on top of the factory default settings in the non-volatile memory.

Abstract: A self-trim circuit provides a technique to trim a CUT (circuit under trim) using a LSB offset to determine the best digital value to trim the CUT. The self-trim circuit is also used to self-test the digital and analog portions of the self-trim circuitry, whereby the existence of a digital stuck at fault condition is detected. A state machine controls a digital stack to couple digital trim data to the CUT and read the output of a comparator circuit that signifies when a proper digital trim value has been used. Thereafter the proper digital trim value is stored into a nonvolatile memory.

Abstract: Circuits and methods to achieve a switch interface circuit for a single pole, single throw (SPST) momentary push-button switch consuming a few tens of nanoamps whilst the push-button switch is closed, having low impedance input path when the switch is open in order to eliminate RFI interference have been achieved. The two states of the push-button switch, open and closed, maintain a low impedance path to one of the power supplies. The supply current is zero when the switch is open and is minimized whilst the switch is closed. The asynchronous edge triggered detection of the switch event allows an extended switch open to closed transition operation.

Abstract: Systems and methods for a front-end circuit receiving a current from a photodiode receiving a signal light and ambient light have been disclosed. In a preferred embodiment the front-end circuit accommodates a photo diode current, generated by a signal light from an infrared LED diode in presence of a current generated by ambient light for a rain-sensing system. The circuit invented has a high dynamic range comprising a programmable transresistance amplifier, a switched capacitor programmable gain amplifier and a switched capacitor fourth-order oversampled sigma-delta A/D converter including an optimized digital filter. Furthermore coarse and fine IDACs are used to successively subtract a current generated by ambient light.

Abstract: A phase-locked loop has a stable high frequency reference oscillator to provide a stable high frequency reference signal that has reference frequency that is a small submultiple of a generated frequency of a voltage controlled oscillator within the phase-locked loop. An adjustable output frequency feedback circuit has with a feedback divide ratio that is approximately the small submultiple and adjusts the feedback ratio such that the generated frequency of the voltage controlled oscillator is locked to a stable low frequency reference input signal. The feedback divide ratio is adjusted as a function of a required ratio change value that is a function of a current phase error of the generated frequency of a voltage controlled oscillator and the stable low frequency reference input signal and a phase error derivative. The phase error derivative is a difference of the current phase error and a previous phase error.

Abstract: Circuits and methods to provide a digital clock signal, which can be instantly halted without glitches and then resumes under control of an asynchronous suspend signal with whole width clock pulses has been achieved. The circuit suspends the clock output in either a high or a low state, instantaneously with the suspend signal. There is no restriction on either the suspend pulse width or position in relation to the input clock. The asynchronous logic implementation is using standard cell logic gates. The circuit functionality is not dependent on the manufacturing technology, i.e. CMOS, bipolar, BI-CMOS, GaAs, etc. implementations are all valid.

Abstract: Systems and methods to achieve a charge pump for generating from single supply voltage energy efficient supply voltages that are symmetrical around ground voltage have been disclosed. The charge pump requires two flying capacitors only. The charge pump generates positive and negative supply voltages following a 1/N ratio of Vdd voltage, i.e. +?Vdd/N, and can be generalized to generate +/?Vdd/2N voltages. This is especially useful for supplying class-G amplifiers.

Abstract: Systems and methods to achieve a charge pump for generating from single supply voltage energy efficient supply voltages having a value of ±? Vdd, ±? Vdd, ±¼ Vdd, ±? Vdd, ±½ Vdd or ±1 Vdd that are symmetrical around ground voltage have been disclosed. The charge pump requires two flying capacitors only. The charge pump generates positive and negative supply voltages following a 1/N ratio of Vdd voltage, i.e. +?Vdd/N, and can be generalized to generate +/?Vdd/2N voltages. This is especially useful for supplying class-G amplifiers with a voltage or power, which is just enough e.g. for an audio signal to be correctly generated at the output of the amplifier.

Abstract: Methods and systems to optimize the adaptation of gamma curve and phase table data to a color LCD STN display anytime by storing these data in a same memory are disclosed. The gamma curve and phase table data are stored in a same read/write memory element; hence allowing the adaptation any time.

Abstract: A modular Gray code counter of arbitrary bit length having identical Gray code counter cells in every bit position. Each cell comprises a Toggle Flop and logic which triggers the Toggle Flop and sets the state of the Gray code counter cell. The two outputs of a cell feed two inputs of the next more significant cell. A parity flip-flop provides odd parity, and as a third input to the cell together with the other two inputs determines the state of the cell.

Abstract: Systems and methods for switched-mode amplifiers having improved harmonic distortion are disclosed. High order in-band filtering is enabled without undue trade-off of distortion due to intermodulation/aliasing. A pre-modulation block is introduced, deployed between a loop filter block and a pulse-width modulation block, performing uniform pulse-width modulation. The pre-modulation block attenuates/removes amplitude dependent high frequency ripples before pulse-width modulation. The pre-modulation block in conjunction with the pulse-width modulation block performs double sampling of the input signals.

Abstract: A CMOS driver test configuration, which allows both leakage current and load current testing, using a single monitor, or current meter, located in a power lead of a tester connected to a power pad servicing the driver circuits. Both leakage testing and load current testing for CMOS drivers is described. The test configuration allows a plurality of driver circuits connected in parallel between power pads to be tested simultaneously. An ESD device, internal to the chip, is used as a load during load current testing in chip testing, and an external load is used during package testing in order to include the bonding means between the chip output pad of the driver and the package I/O pin in the current path during load current testing.

Abstract: Systems and methods to achieve a logarithmic digital-to-analog converter (DAC), which is easy to be implemented, and requiring reduced chip space have been disclosed. The logarithmic DAC is created by a simple and easy to scale linear DAC, which is linearly scaling a predefined voltage range. The output voltage of the linear DAC is converted to a logarithmic current value directly by the voltage-current characteristic of an integrated diode.

Abstract: A method and implementation is described by which I/O input and output circuitry of a CMOS chip are measured without the need to probe the chip. Output driver transistors are used to provide marginal voltages to test input circuits, and the output driver transistors are segmented into portions where a first portion is used to provide a representative “on” current, which is coupled to a test bus that is further connected to a current comparator circuit contained within the chip. Both leakage and “on” current of the driver transistors is measured using segmented driver transistors. The output of the current comparator circuit is connected to a test scan register or to a test output from which test results are obtained digitally. The testing techniques are also applicable for other semiconductor devices.

Abstract: Systems and methods to achieve an IC audio volume control requiring minimum silicon area and having an accurate volume control gain setting are disclosed. A resistive element in form of a R/2R ladder is deployed between an output node of an operational amplifier and an input node of the circuit. All resistors of said resistive element are unit resistors having a same resistance, wherein said unit resistors are arranged in parallel or series combinations to achieve a resistance desired. A first number of switches are deployed between nodes of the R/2R ladder and an inverting input of the operational amplifier. Furthermore a second number of switches are deployed between nodes within resistor units of the R/2R ladder and the inverting input. The circuit invented could have a single input or a differential input, or a single ended output or a differential output.

Abstract: An integrated circuit for a charge pump with a charge stage and a pump stage and a single High-Voltage PMOS (HVPMOS) transistor as the main switch for each stage and two times two minimum HVPMOS transistors in series as a bulk switch with fixed bulk connections, where the minimum HVPMOS transistors are smaller sized transistors than the transistors of the main switch. The bulk of the main switch is switched synchronously to the voltage node of the HVPMOS transistor of the main switch to force the bulk voltage (VB) to be equal or larger than either the source voltage (VS) or the drain voltage (VD). Two non-overlapping clock signals are used to trigger the HVPMOS transistors of the charge and pump stage.

Abstract: An integrating amplifier on an IC, which comprises a feedback loop using an external device as an integrating capacitor, has added a second feedback loop that provides an additional current to the input of the amplifier, which current can be used to increase the input range of the charge that can be measured without needing another external capacitor or pad.

Abstract: Systems and methods using the same to achieve a tri-level multi-bit delta-sigma DAC having reduced power consumption and voltage droop have been achieved. A new rotation-based first order noise-shaping Dynamic Element Matcher (DEM) technique for use with 3-level unit elements have been disclosed. Reduced reference loading has been achieved when the tri-level DEM scheme is applied to switched capacitor implementations in particular. Furthermore a differential switched-capacitor DAC implementation, which enables use of the DEM technique is disclosed. The invention allows reduced circuit complexity required to implement a N-bit DAC when constructed using 3-level unit elements.

Abstract: Circuits and methods to achieve a buck-boost converter, capable to achieve a constant output voltage by pre-charging of an inductor if the input voltage is close to the output voltage has been achieved. The prior art problem of output voltage variations occurring while the input voltage is close to the output voltage is avoided. In case the input voltage is lower than a defined threshold voltage or the duty cycle exceeds a defined maximum allowable level, the inductor of the converter is pre-charged followed by boosting of the energy of the inductor to the output of the converter. In both modes the control loops of the buck converter can be used for buck duty cycle control. The duration of the pre-charge depends upon the level of the input voltage, the lower the input level is the longer is the pre-charge performed.