Abstract: A high voltage digital output driver with dynamically biased cascode transistors is disclosed. The cascode transistors are dynamically self-biased via capacitors from the output voltage. The dynamic self-biasing doesn't require any switching means. The output-voltage can be increased by adding additional self-biased cascode transistors. The static current consumption in low-state for each individual driver on a same chip is minimal because only one resistor string consuming static current is required for all similar output drivers.

Abstract: Circuits and methods to achieve a regulated analog switch being capable to provide an output-voltage not exceeding a defined limit are disclosed. In a preferred embodiment a car battery provides a supply voltage up to 40 Volts, wherein a load must not have an output voltage higher than 22 Volts. The drain-source ON-resistance of the switch, realized by a high-voltage MOSFET, is kept to a minimum. The voltage regulation of the preferred embodiment is performed by a single stage operational amplifier and a two-stage amplifier having Miller compensation.

Abstract: A circuit where the same amplifiers and the same volume adjustment circuitry are used for the ringer mode as well as for the audio mode of a mobile phone is achieved. The volume adjustment in the audio and ringer mode is provided by a precise amplitude setting via the gain control stages of an inverting voltage amplifier used in a bridge circuit through a current-voltage conversion. This volume adjustment circuit avoids the high power dissipation of a volume control through pulse width modulation (PWM) and avoids the risk of over-and undershooting of the amplifier's output signal due to a high slew rate in combination with the inductance of the loudspeaker. The current-voltage conversion is performed by a series of resistors activated by a series of correspondent switches. High impedance current less sense paths are eliminating the parasitic effect of the resistance of low cost standard switches to adjust the volume of the loudspeaker in the audio and the ringer mode.

Abstract: An integrated battery package, that contains semiconductor chips, for example to control and regulate battery charging and to monitor the package operation, uses a single lead frame to interconnect several internal chips, to internally connect said control chips to the battery and to connect the whole package assembly externally. The invention eliminates the need for any additional connecting mechanism. The invention uses established production processes. A molding process, similar to plastic chip encapsulation, encloses the battery controlling chips and forms at the same time the body of the battery package. An additional cover, sealed to said body, closes the battery package.

Abstract: Liquid crystal display (LCD) systems and related methods to achieve reduced resistance of the connections between the display controller device and MLA common sub-groups or groups of signal lines of the display unit avoiding differences of contrast between adjacent lines of an LCD display unit have been achieved. In a preferred embodiment of a Multiple Line Addressing (MLA) Super Twisted Nematic (STN) LCD driver the lines of the common sub-groups are interlaced alternately from both sides of the display control device to the correspondent sides of the display unit in a way that the uppermost common sub-group is driven from a first side of the display control device, the second uppermost sub-group is driven from the side opposite to said first side, the third uppermost sub-group is driven from said first side again and so on. The number of lines per common sub-group is variable. One advantage of the interlaced scheme invented is that the overall glass routing distance is shorter hence reducing resistance.

Abstract: A method to form a very low resistivity interconnection in the manufacture of an integrated circuit device is achieved. A bottom conductive layer is formed overlying a substrate. The bottom conductive layer creates a first electrical coupling of a first location and a second location of the integrated circuit device. A dielectric layer is formed overlying the bottom conductive layer. A top conductive layer is formed overlying the dielectric layer. The top conductive layer is coupled to the bottom conductive layer through openings in the dielectric layer to form a second electrical coupling of the first location and the second location. A metal wire is bonded to the top conductive layer to form a third electrical coupling of the first location and the second location to complete the very low resistivity interconnection in the manufacture of the integrated circuit device.

Abstract: A charge pump circuit with a regulated charge current where the amount of current flowing into the flying capacitor depends on the magnitude of the output voltage error, using an OTA to convert the output voltage error into a current. Thus the flying capacitor is not charged when the output load is very low or when the output voltage error is minimal. Voltage overshoots are reduced by a stop circuit which forces pulse skipping and which inhibits the charging of the flying capacitor. Current limiting devices further limit the charge current into the flying capacitor. Full short-circuit protection is provided in one preferred embodiment by current limiting the driver stage of the charge pump circuit. Except for pulse skipping, the charge pump runs at a constant frequency supplied by a clock.

Abstract: A method and a circuit are given, to implement and realize power saving Sense Electronics Endowed (SEE) memory using modified memory read cycles, named as Smart Memory Readout (SMR). In an SMR-mode read cycle, the memory is only active a small fraction of a clock cycle thus saving power. In this small fraction where the memory is enabled by SMR-mode read, the memory content is read to a shadow register and held until read by the microcontroller. Said circuit and method are designed in order to be implemented with a very economic number of components, capable to be realized with modern integrated circuit technologies.

Abstract: A voltage controlled variable capacitor, formed of a larger number of fixed capacitor segments and a corresponding number of switching elements, linearly switches on each switching element, one after the other. Several techniques are disclosed to have only a minimum number of switching stages being in the active mode-of-change at any one time with a minimum overlap. The arrangement achieves a nearly linear change of capacitance versus tuning voltage change, while resulting in high Q-factor due to the low RDSon and high RDSoff of the fully switched stages.

Abstract: A circuit and method are given, to realize a loudness control for mobile phone earpieces and speakers with the help of a proximity sensor, which is realized as an infrared photo-electric guard circuit, where only very few external parts are needed. As a novelty here, the necessary photo sensors are integrated onto a single chip. To form the photodiodes within a single IC together with the other circuit elements are much less expensive. Using the advantages of that solution the circuit of the invention is manufactured with standard CMOS technology and only very few discrete external components. This solution reduces also power consumption and manufacturing cost.

Abstract: This invention provides a method and an apparatus for saving power dissipation during the testing and evaluation of liquid crystal display LCD panels. In addition, this invention provides a method and apparatus of the changing of the order of backplane and segment addressing to reduce the power consumed by LCD panels. The method includes the step of interlacing the access of common or backplane addresses to an LCD. The LCD power saving method also includes the interlacing the access of the RAM data driving the LCD segment drivers. The segment address signals are developed from data read out of a random access memory, RAM. The segment address signals are activated such that alternating LCD panel locations are written with ones and zeros in a checkerboard pattern so as to stress the LCD panel in the worst case. This method provides for the saving of power dissipation during testing and evaluation by reducing the amount of segment switching from once every backplane cycle to once every frame.

Abstract: Circuits and methods to achieve a low-noise and low offset continuous sigma-delta modulator used e.g. for battery management are disclosed. Continuous integration of input is enabled by special switching principle of three parallel integrators. Precharging of integrator output in so called pre-run mode minimizes integrator leakage and non-ideal effects by connecting a Gm in pre-run mode either to input voltage or to a reference voltage depending this Gm is being used in a following clock period. Parasitic effects due to switching at first integration capacitor are minimized by using buffer amplifiers tracking the voltage on integration capacitors.

Abstract: A circuit and a method are given, to realize an electronic system for combined usage at differing voltage ranges as defined by a low-voltage range for operating standard CMOS devices and a high-voltage range exceeding said standard CMOS low-voltage operating range significantly by multiples and thus necessarily utilizing input ports with an intrinsic high-voltage protection feature. Said circuit and method are designed in order to be implemented with a very economic number of components, capable to be realized with standard modern integrated circuit technologies in CMOS technology.

Abstract: A method for dynamically adapting the biasing current for a fast switching CMOS comparator is achieved. The difference of the two input signals of said comparator controls the comparator's biasing current, where the biasing current is high only when the difference is low and the comparator's switching is likely to happen and where the biasing current is kept low at other times. In a current mirroring circuit, the voltage difference at the comparator inputs controls the mirroring ratio. The biasing current reaches its maximum when the input voltage difference approaches zero. Once the input voltage difference crosses zero and continues to change in the same direction as before, that is after the polarity of the voltage difference changed, the control mechanism alternates the connection of the comparator input signals to the current controlling elements, in order to now reduce the current with a further increase of the voltage difference.

Abstract: Methods and circuits for chain ring oscillators having a constant duty cycle and being insensitive to ground noise have been disclosed. The ring oscillator generates n outputs with 360°/n phase shift and each stage is delayed by T 2 × n . The output of a suitable stage is selected so that a digital XOR-gate, using the output of a selected stage and the output of the nth stage, eliminates variations of the duty cycle caused by temperature and process variations. In case a 50% duty cycle is desired the stage number N of the selected stage can be calculated using the equation N=(n?1)/2. The duty cycle can be varied by selecting the output of another gate. A D-flipflop, clocked by the output of the XOR-gate removes noise from the clock pulses.

Abstract: A central processor unit (CPU) accesses memory to read and write data and to read and execute program instructions. A problem arises when accessing slower Flash or electrically programmable read only memory (EPROM) with a faster CPU. A method and system has been devised which uses interleaving techniques and memory sub-sections. A memory interlace controller interfaces a faster CPU to several sub-sections of slower memory. The memory interlace controller interlaces the access of the slower memory and thus optimizing the CPU system speed.

Abstract: A communication device such as a cellular or wireless telephone handset has a light display, such as handset cover light or display backlight, synchronized to audio signals from multiple audio sources such as a microphone or AM/FM receiver. The communication device further includes an audio to illumination conversion apparatus for modulating the light display in response to the audio signal. The audio to illumination conversion apparatus has a plurality of audio filter circuits for filtering the audio signal to restrict frequency content of the audio signal to a pass-band. Multiple integration circuits generate an energy content signal indicating an energy level within the pass-band and for the whole spectrum of the audio signal. An illumination modulator generates a modulation pattern for the light display in response to the energy content signals from a predefined light show.

Abstract: Circuits and methods to sense the current through a coil of an integrated switching converter, applicable to boost and to buck converters, have been achieved. The present invention uses a “replica biasing” technique to avoid a resistor for current measurement. The current through a pass device is mirrored into a replica, having a scale of n and being much smaller in size, of said pass device. The current through the replica is mirrored to another branch of the circuit and back again to achieve a fast stabilization of the current. The current through the replica is mirrored again to an output branch of the circuit, which conducts exactly a fraction 1/n of the current flowing through the pass device. The self-biasing current loop of the invention adapts quickly to the actual current level through the pass device of the switching converter. Accuracies better than 5% are achieved over a wide range of dynamic range.

Abstract: Circuits and methods to provide an LDO output stage implemented with low-voltage devices and still allowing higher voltage levels have been achieved. The output stage has been built using two low voltage MOS devices in series. During the time the regulator is in active mode the second MOS device acts as a small resistor in series to the pass device. During power down this second device actively protects the MOS pass device and itself from high voltage stress levels. This is achieved by a robust regulating mechanism that compensates leakage currents. These leakage currents normally determine the different potentials of the output stage during power down. Although the second transistor presents a resistive obstacle during active mode the total chip area required is smaller compared to a single pass device tolerating e.g. 5 Volts.

Abstract: Circuits and related methods for switched step-down and boost DC-to-DC converters have been achieved. Said DC-to-DC converters comprise an inductor current sensing and limiting circuit to prevent the inductor current to exceed a defined limit. Said current sense circuit is using the voltage on the on-state source-to-drain resistance of a power switch to monitor the inductor current. Said voltage is amplified and serves as input of a regulator. Said regulator, being connected via one or more gate controllers to the gates of said power switches, controls the ON/OFF state of said power switches by pulse-width-modulation. Said power switches are switched ON/OFF if the current exceeds a defined limit. After a defined time period said power switches are switched on again. Gate controllers keep the power switch in an operating region having a stable source-to-drain resistance while said power switch is ON.