Patents Assigned to Digit
  • Publication number: 20250139013
    Abstract: Redundancy bits can be used to more effectively manage address translation cache (ATC) in data storage devices. The data storage device maintains a table of redundancy bits. When a request for an address translation arrives, the redundancy bits are calculated and compared to redundancy bits in the table. If there is a match, then the relevant ATC entry is retrieved and compared to the untranslated addresses. The same process is repeated for each redundancy bits match until finding a match in the ATC. In so doing, the translated address can be requested much earlier than normal by requesting the translated address upon the redundancy bits not matching. The earlier retrieval reduces throughput of the memory device without reducing performance. Furthermore, the unique structure of the internal ATC allows most of the ATC to be located in SRAM/DRAM while simply the redundancy bits are stored in flops.
    Type: Application
    Filed: November 1, 2023
    Publication date: May 1, 2025
    Applicant: Western Digital Technologies, Inc.
    Inventor: Shay BENISTY
  • Publication number: 20250142348
    Abstract: Systems, methods, and apparatuses for providing optimization of network resources. The system is operable to monitor the electromagnetic environment, analyze the electromagnetic environment, and extract environmental awareness of the electromagnetic environment. The system extracts the environmental awareness of the electromagnetic environment by including customer goals. The system is operable to use the environmental awareness with the customer goals and/or user defined policies and rules to extract actionable information to help the customer optimize the network resources.
    Type: Application
    Filed: January 2, 2025
    Publication date: May 1, 2025
    Applicant: Digital Global Systems, Inc.
    Inventor: Armando Montalvo
  • Publication number: 20250135928
    Abstract: A bidirectional on-board charger includes a direct current bus, two bus capacitors, a power factor correction circuit, and a controller. The power factor correction circuit includes: a first bridge arm; and three second bridge arms, separately connected in series between the positive electrode and the negative electrode of the direct current bus. The controller is configured to: control the first switch (K1) to be turned off, and control at least one of the second bridge arms to output a direct current to charge a power battery; or control the first switch (K1) to be turned on, and control a midpoint of at least one of the second bridge arms to output an alternating current to supply power to an alternating current load. A Vehicle power system and an electric vehicle are further disclosed. The charger reduces circuit costs.
    Type: Application
    Filed: January 3, 2025
    Publication date: May 1, 2025
    Applicant: Huawei Digital Power Technologies Co., Ltd.
    Inventors: Zhigang Liang, Yuandong Meng, Hui Ni
  • Publication number: 20250139021
    Abstract: A computing device includes a plurality of computing nodes, a plurality of component units, and a control unit. The control unit includes a plurality of first interfaces and at least one second interface, each computing node is connected to one first interface, and the at least one second interface is electrically connected to the component units. The control unit is configured to obtain management information and store the management information. The management information includes at least one of component working information of each component unit or node working information of each computing node. The computing node is configured to send a query request to the control unit, and obtain management information corresponding to the query request from the control unit. In the present application, related information of the computing nodes and the component units are conveniently stored and exchanged within the computing device.
    Type: Application
    Filed: December 30, 2024
    Publication date: May 1, 2025
    Applicant: xFusion Digital Technologies Co., Ltd
    Inventors: Xusheng Yuan, Binfeng Wang, Xuan Lv
  • Publication number: 20250140318
    Abstract: As block sizes in NAND memory continue to increase in size and density, in can be useful to access less than all of the block, such as sub-block or subset of the blocks NAND strings, in order to reduce read disturbs, reduce power consumption, and increase operating speeds. Although this sort of separation of sub-block can be achieved by independently biasable select gates, the sort of select gate structure can face processing difficulties, particularly at the source side of three dimensional NAND structures. To avoid these difficulties while still providing individually selectable sub-blocks, the following introduces word line based selectors, where multiple word lines of a blocks are programmed with different sets of threshold voltages, allowing them to be biased for individual access of sub-blocks.
    Type: Application
    Filed: November 1, 2023
    Publication date: May 1, 2025
    Applicant: Western Digital Technologies, Inc.
    Inventors: Motoo Ohaga, Shinsuke Yada, Naohiro Hosoda, Hiroyuki Ogawa
  • Publication number: 20250139395
    Abstract: A memory card is provided with various pad layouts to prevent a data signal pad from contacting a power contact in a host during insertion and removal of the memory card. The memory card can have a form factor and features that accommodate a relatively-large memory with relatively-high performance and accompanying thermal conditions. An efficient card lock mechanism is also provided.
    Type: Application
    Filed: December 19, 2023
    Publication date: May 1, 2025
    Applicant: Western Digital Technologies, Inc.
    Inventors: Yoseph Pinto, Jegathese Dhanachandra Prakash, Nandha Kumar Mohanraj, Satish Kammar
  • Publication number: 20250139344
    Abstract: An apparatus includes one or more control circuits configured to connect to a plurality of nonvolatile memory cells. The control circuits are configured to count a number of pulses sent to switches of a charge pump, record a count of the number of pulses sent to the switches and send the count of the number of pulses in response to a request for the count of the recorded number of pulses.
    Type: Application
    Filed: October 26, 2023
    Publication date: May 1, 2025
    Applicant: Western Digital Technologies, Inc.
    Inventors: Keyur Payak, Zhenqian Jian, Khin Htoo, Tushar Negi, Primit Modi
  • Patent number: 12289601
    Abstract: Systems, methods, and apparatuses for providing dynamic, prioritized spectrum utilization management. The system includes at least one monitoring sensor, at least one data analysis engine, at least one application, a semantic engine, a programmable rules and policy editor, a tip and cue server, and/or a control panel. The tip and cue server is operable utilize the environmental awareness from the data processed by the at least one data analysis engine in combination with additional information to create actionable data.
    Type: Grant
    Filed: August 22, 2024
    Date of Patent: April 29, 2025
    Assignee: Digital Global Systems, Inc.
    Inventor: Armando Montalvo
  • Patent number: 12287852
    Abstract: Systems and methods of sensor data fusion including sensor data capture, curation, linking, fusion, inference, and validation. The systems and methods described herein reduce computational demand and processing time by curating data and calculating conditional entropy. The system is operable to fuse data from a plurality of sensor types. A computer processor optionally stores fused sensor data that the system validates above a mathematical threshold.
    Type: Grant
    Filed: December 20, 2024
    Date of Patent: April 29, 2025
    Assignee: Digital Global Systems, Inc.
    Inventor: Armando Montalvo
  • Patent number: 12289603
    Abstract: Systems, methods, and apparatuses for providing optimization of network resources. The system is operable to monitor the electromagnetic environment, analyze the electromagnetic environment, and extract environmental awareness of the electromagnetic environment. The system extracts the environmental awareness of the electromagnetic environment by including customer goals. The system is operable to use the environmental awareness with the customer goals and/or user defined policies and rules to extract actionable information to help the customer optimize the network resources.
    Type: Grant
    Filed: October 23, 2024
    Date of Patent: April 29, 2025
    Assignee: Digital Global Systems, Inc.
    Inventor: Armando Montalvo
  • Patent number: 12289602
    Abstract: Systems, methods, and apparatuses for providing optimization of network resources. The system is operable to monitor the electromagnetic environment, analyze the electromagnetic environment, and extract environmental awareness of the electromagnetic environment. The system extracts the environmental awareness of the electromagnetic environment by including customer goals. The system is operable to use the environmental awareness with the customer goals and/or user defined policies and rules to extract actionable information to help the customer optimize the network resources.
    Type: Grant
    Filed: September 12, 2024
    Date of Patent: April 29, 2025
    Assignee: Digital Global Systems, Inc.
    Inventor: Armando Montalvo
  • Patent number: 12288608
    Abstract: A system for recording, storing and processing diagnostic information, including: a computer implementing a computer-readable media including digital data and ground truth; a registry constructed and arranged to store and associate transactions or accesses on the data; and a machine learning system that considers each learning step modification a microtransaction for the data used in that step and which is recorded in the transaction registry. Other embodiments of this aspect include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the methods.
    Type: Grant
    Filed: March 25, 2024
    Date of Patent: April 29, 2025
    Assignee: Digital Diagnostics Inc.
    Inventor: Michael D. Abramoff
  • Patent number: 12287851
    Abstract: Systems and methods of sensor data fusion including sensor data capture, curation, linking, fusion, inference, and validation. The systems and methods described herein reduce computational demand and processing time by curating data and calculating conditional entropy. The system is operable to fuse data from a plurality of sensor types. A computer processor optionally stores fused sensor data that the system validates above a mathematical threshold.
    Type: Grant
    Filed: January 15, 2025
    Date of Patent: April 29, 2025
    Assignee: Digital Global Systems, Inc.
    Inventor: Armando Montalvo
  • Patent number: 12287969
    Abstract: Systems and methods for dynamic throttling of input/output queues in data storage device arrays are described. Data storage devices are connected through the slots and corresponding lanes of a storage interface switch. A storage controller uses a delay inserted between host submission queues and backend submission queues to manage the priority of host storage commands using slot groups.
    Type: Grant
    Filed: August 3, 2023
    Date of Patent: April 29, 2025
    Assignee: Western Digital Technologies, Inc.
    Inventors: Rahul Gandhi Dhatchinamoorthy, Kumar Ranjan, Senthil Kumar Veluswamy
  • Patent number: 12289604
    Abstract: Systems, methods, and apparatuses for providing optimization of network resources. The system is operable to monitor the electromagnetic environment, analyze the electromagnetic environment, and extract environmental awareness of the electromagnetic environment. The system extracts the environmental awareness of the electromagnetic environment by including customer goals. The system is operable to use the environmental awareness with the customer goals and/or user defined policies and rules to extract actionable information to help the customer optimize the network resources.
    Type: Grant
    Filed: October 25, 2024
    Date of Patent: April 29, 2025
    Assignee: Digital Global Systems, Inc.
    Inventor: Armando Montalvo
  • Publication number: 20250130716
    Abstract: Instead of a system with no awareness to the specific properties of the described system files, such as atomicity of different types of system files, utilize the special characteristics of the corresponding system files to optimize storage handling. A host marks a certain logical block address (LBA) range as belonging to an atomic file. That entire range will be treated as a single atomic unit. Conversely, an LBA range being used to append to a log file may have very small atomic units, allowing for incremental updates without changing the atomicity of the rest of the media. When a write command is passed, the write command will have a certain length. Depending on the length of the write command, the device can disassemble the write command into smaller write sectors of the smallest possible write portion. The device will then write the small write portions to a storage location, while keeping an atomic principle of each of the small write portions.
    Type: Application
    Filed: October 18, 2023
    Publication date: April 24, 2025
    Applicant: Western Digital Technologies, Inc.
    Inventors: Judah Gamliel HAHN, Ariel NAVON, Alexander BAZARSKY, Shay BENISTY
  • Publication number: 20250133001
    Abstract: Instead of maximizing the possible bandwidth of device, utilize time slice credits (TSC), to ensure bandwidth average over a sliding window. When the average is ensured over a sliding window, the device should not care when the host decides to sample a 100 mSec for example, as the average will always be correct. By utilizing set percentage of predetermined allotment for the average bandwidth requirement, the system can give out credit on a predetermined interval. The credit is given out based on usage and once credit is depleted, data cannot be sent until more credit is accumulated. When data is not sent, the system is given a chance to accumulate credit to increase the amount of data sent. Once credit is at a level high enough to send data the device will send the data, but not at a speed that will surpass the average bandwidth requirement.
    Type: Application
    Filed: October 18, 2023
    Publication date: April 24, 2025
    Applicant: Western Digital Technologies, Inc.
    Inventors: Amir SEGEV, Shay BENISTY
  • Publication number: 20250132205
    Abstract: A semiconductor wafer is prepared with the silicon {111} crystalline plane parallel to the major surfaces of the wafer. After preparation of the wafer with the desired {111} crystalline plane orientation, integrated circuit semiconductor dies may be defined in one of the major surfaces of the wafer. Stress defects may then be formed in the wafer in a {111} crystalline plane at a depth corresponding to the final thickness of the wafer. Cracks propagate from the stress defects in the plane of the stress defects, effectively cleaving the wafer in two at the desired finished thickness of the wafer.
    Type: Application
    Filed: October 24, 2023
    Publication date: April 24, 2025
    Applicant: Western Digital Technologies, Inc.
    Inventors: Fan Ye, Xinnan Wang, Huo Liang Chen, Shuqian Zhang, Weiting Jiang
  • Publication number: 20250133410
    Abstract: Systems, methods, and apparatuses for providing dynamic, prioritized spectrum utilization management. The system includes at least one monitoring sensor, at least one data analysis engine, at least one application, a semantic engine, a programmable rules and policy editor, a tip and cue server, and/or a control panel. The tip and cue server is operable utilize the environmental awareness from the data processed by the at least one data analysis engine in combination with additional information to create actionable data.
    Type: Application
    Filed: December 20, 2024
    Publication date: April 24, 2025
    Applicant: Digital Global Systems, Inc.
    Inventor: Armando Montalvo
  • Publication number: 20250131964
    Abstract: To reduce Icc spikes during the operation of a non-volatile memory device, different block decoding parameters can be used based on whether a block is open or closed. For blocks that are open or in other high Icc conditions, such as first read, the timing for the block decode control signals, the block decode voltage levels, or a combination of these can be used to lower Icc spikes.
    Type: Application
    Filed: October 23, 2023
    Publication date: April 24, 2025
    Applicant: Western Digital Technologies, Inc.
    Inventors: Abu Naser Zainuddin, Jiahui Yuan, Sai Gautham Thoppa