Abstract: In order to provide a thermal coupling between a heat source and a heat sink, an interleaved-fin connector is provided. The connector comprises first and second substrates. The first substrate includes a first surface. A plurality of first channels are etched on the first surface to form a plurality of first fins and a first base. The first base can be thermally engaged with the heat source. The second substrate includes a second surface having a plurality of second channels etched therein. The second channels form a plurality of second fins and a second base. The second base can be thermally engaged with the heat sink. The first and second fins providing a thermally conductive path from the heat source to the heat sink when interleaved with each other.

Abstract: A computer includes a multi-bit analog-to-digital converter, which is mounted within the computer's housing and has a digital output operatively connected to a bus port of the computer's processor. The computer also includes a local passive identification network that has a first node operatively connected to an analog input of the converter and further nodes respectively electrically connected to pins of a multi-contact local interface connector. A passive peripheral device identification network including a plurality of nodes each electrically connected to a multi-contact peripheral identification connector can mate with the multi-contact local connector.

Abstract: A computerized method enables an audience to synchronously interact with a broadcast program in realtime. A broadcast clock of a broadcast system is synchronized to a standard time. A server clock of a server computer is synchronized to the standard time using a network timing protocol. A client computer clock of a client computer is synchronized to the server clock. The program is broadcast synchronously to the broadcast clock. Web pages are provided by the server computer to the client computer. Responses generated by the client computer are time-stamped according to the synchronized time of the client computer so that the responses can be time-correlated to segments of the program.

Abstract: A technique involves broadcasting a pulse signal to synchronize oscillating signals used by multiple power supplies to provide output voltages. The technique involves charging and discharging respective capacitors of the multiple power supplies at respective rates to provide the oscillating signals. Each of the respective capacitors is charged until a voltage across that capacitor reaches a respective upper threshold and subsequently discharged until the voltage across that capacitor reaches a respective lower threshold. The technique further involves broadcasting, from at least two of the power supplies, a pulse signal to a synchronization connection coupled to each of the respective capacitors to modify the respective rates for charging and discharging the respective capacitors based on the pulse signal such that oscillating signals become synchronized.

Abstract: An apparatus for use in a computer has a network interface subsystem having power applied thereto when power is removed from other components of the computer. A receiver in the network interface subsystem receives a packet directed to the computer from the network, and in response to receipt of a selected packet, restores power to the other components of the computer. Upon restoration of power to the other components of the computer, a signalling device reports status of at least one of the other components of the computer to the network interface subsystem. A transmitter in the network interface subsystem sends, in response to the signalling device, a status packet onto the network giving a status of the computer in the event that a component is not functional, following restoration of power to the other components of the computer.

Abstract: A multiplier in a floating point processor includes a circuit to determine for each bit of the multiplier operand a 3 times booth recode and a booth recode multiplier array which implements a 3 times booth recode multiplication. The multiplier includes logic to determine a fast sign extend to replace bit positions shifted in the array as well as a rounding adder to provide a rounded result while determining the final result from the booth recode multiplier. The multiplier also includes a circuit to determine a contribution to the final multiplication result from a lower order product with out forming the entire product.

Abstract: A memory of a computer system is partitioned into a plurality of allocable blocks. Subsets of the allocable blocks are organizing into a plurality of heaps, each heap having a different designated subset of the allocable blocks. The sizes of the allocable blocks of each of the heaps are determined by scaling a progression of numbers, preferably computed as an integer power of two, by a selected integer different for each heap. The scaled blocks, when allocated, can be used to store a segment of data to be processed by the computer system.

Abstract: A computer having a case has a connection point for a communications line, where the connection point is accessible from outside the case. A socket receives a standard communications hardware card, the hardware card having a first receptacle to electrically connect to circuits of the computer, and the hardware card having a second receptacle to electrically connect to an exterior electrical circuit, the exterior electrical circuit usually being exterior to the case. A mounting means attaches the socket to the computer, the mounting means positioning the socket to facilitate a connection to the second receptacle of the hardware card, the connection located wholly internal to the case. A multi wire connector electrically connects to the second receptacle of the hardware card, and the multi wire connector is located wholly internal to the case.

Abstract: A duplicate cache tag store, accessible to a graphics processor and to devices connected to the I/O bus without creating traffic on the system bus. Any entry into, or displacement from, the CPU cache tag store is also entered into, or displaced from, the second cache tag store.

Abstract: Provided is a method for estimating statistics of properties of interactions among instructions processed in a pipeline of a computer system, the pipeline having a plurality of processing stages. Instructions are fetched into a first stage of the pipeline. A set of instructions are randomly selected from the fetched instructions, a subset of the set of selected instructions concurrently executing with each other. A distances between the set of selected instructions is specified, and state information of the computer system is recorded while the set of selected instructions is being processed by the pipeline. The recorded state information is communicated to software where it is statistically analyzed for a plurality of sets of selected instructions to estimate statistics of the interactions among sets of selected instructions.

Abstract: A computer-implemented method determines the resemblance of data objects such as Web pages. Each data object is partitioned into a sequence of tokens. The tokens are grouped into overlapping sets of the tokens to form shingles. Each shingle is represented by a unique identification element encoded as a fingerprint. A minimum element from each of the images of the set of fingerprints associated with a document under each of a plurality of pseudo random permutations of the set of all fingerprints are selected to generate a sketch of each data object. The sketches characterize the resemblance of the data objects. The sketches can be further partitioned into a plurality of groups. Each group is fingerprinted to form a feature. Data objects that share more than a certain numbers of features are estimated to be nearly identical.

Abstract: A compiler-loader system enables the creation of different loaded executable images in target computers complying with different versions of an instruction-set architecture, the different images being created from a single executable program on secondary storage. The compiler generates an executable program containing a routine executable on both versions of the target computers, and also containing an architecture entry with (i) an address of the program location from which the routine is called, (ii) an instruction executable on only one version of the target computers that performs the same function as the routine but with superior performance, and (iii) a value indicating which version of the target machines the instruction can be executed on. The loader determines whether the target machine can execute the instruction, and if so replaces the subroutine call appearing at the address in the architecture entry with the instruction appearing in the architecture entry.

Abstract: A time-based and event-based interrupt frequency mitigation scheme is provided. A holdoff event counter is programmed to count a holdoff event count corresponding to a number of interrupts. A holdoff timer is programmed to time a holdoff interval representing the time period to elapse before the generation of an interrupt request to the host system can occur. When a data transfer request associated with the transfer of data from or to the host system is serviced and results in the occurrence of an interrupt event, the holdoff event counter is modified by one. If either the holdoff event counter or the holdoff timer has expired and the interrupt is enabled, an interrupt request to the host system is generated. In response to such interrupt request generation, the interrupt is processed and both the holdoff event counter and the holdoff timer retriggered.

Abstract: The invention includes an apparatus and method for buffering data transmitted by a processor and received by an I/O device via a memory and buses. The memory arranged at a plurality of levels includes a lower level of the memory operating faster than a higher level of the memory. A plurality of ring buffers are allocated at different levels of the memory and available buffers at a lowest possible level of the memory are preferentially selected as write buffers to store data transmitted by the processor. The apparatus includes a first level of the memory arranged on an integrated circuit with the processor, a second level of the memory arranged in an off-chip cache, and a third level of the memory arranged in a dynamic random access memory. Read buffers are selected to store data to be received by the I/O device. Stored control values indicate the order for selecting the read buffers and are used by the processor to select the write buffer.

Abstract: An apparatus and method for counting event signals generated by a computer system is described. The event signals are indicative of the performance of the computer system. Programmable logic enhances the functionality of performance counters by enabling the system user to specify, during the execution of an application program, which event signals to count. The system user can dynamically configure the programmable logic to select a subset of the event signals generated by the computer system, and to combine the selected subset of event signals to generate a new event signal that can be counted. Other new event signals can be generated by the programmable logic from the selected subset of event signals. A user of the computer system can dynamically make the selection of any one of the new event signals for counting.

Abstract: A processor includes an execution pipeline and a retire unit coupled to an end of the execution pipeline. The processor executes instructions of a program. An apparatus for collecting performance data while the instructions are executing includes a register coupled to the retire unit of the processor. Means are provided for incrementing the register whenever an instruction is retired from the execution pipeline. In addition, the apparatus includes means for generating an interrupt to an interrupt handler whenever the register is incremented to a predetermined value.

Abstract: In a relaxed bus protocol for transferring bursts of data from a slow device to another device, a predictor generates an advance signal. The advance signal is used to load next data into an output register of the slow device, the next data can then be transferred to the other device. A validator/corrector receiving a ready signal from the second device, the validator/corrector determines that the advance signal is correctly generated by the predictor. Heuristics and a higher level protocol adjust the size and frequency of the bursts of data to achieve optimal performance, and maintain correctness of transmitted data.

Abstract: A method of scheduling program instructions for execution in a computer processor comprises fetching and holding instructions from an instruction memory and executing the fetched instructions out of program order. When load/store order violations are detected, the effects of the load operation and its dependent instructions are erased and they are re-executed. The load is associated with all stores on whose data the load depends. This collection of stores is called a store set. On a subsequent issuance of the load, its execution is delayed until any store in the load's store set has issued. Two loads may share a store set, and separate store sets are merged when a load from one store set is found to depend on a store from another store set. A preferred embodiment employs two tables. The first is a store set ID table (SSIT) which is indexed by part of, or a hash of, an instruction PC.

Abstract: A method and apparatus for enabling access of a document on a remote network device by a local computer includes an interceptor for intercepting a request (from a web browser on the local computer system) for accessing the document. The interceptor responsively ascertains whether the local computer is connected to a network and, if connected to the network, downloads the document into memory of the local computer system. If the local computer is not connected to the network, the method and apparatus locates the document in the local memory of the local computer. Once downloaded or located, whichever the case may be, the document may be utilized by the user, such as by displaying the document on a display device.

Abstract: A debugger for debugging, from a central location (e.g., a user terminal 13), jobs or processes running on one or more remote units (11) connected to the user terminal (13) via a communication network (15). The user terminal (13) includes a debugger (21) that receives and interprets debug commands produced by a keyboard and display console (19). The debug commands fall in any one of three categories--debug commands directed to the user terminal (USER TERMINAL CONTROL commands); debug commands directed to a particular remote unit (REMOTE UNIT CONTROL commands); and, debug commands directed to a specific job or process of multiple jobs or processes running on a particular remote unit (LOCAL JOB/PROCESS commands). The USER TERMINAL CONTROL commands are executed at the user terminal (13). The REMOTE UNIT CONTROL commands and LOCAL JOB/PROCESS commands are transmitted to the remote units (11) via the communication network (15).