Patents Assigned to Digital Equipment Corporation
  • Patent number: 6078565
    Abstract: A relatively small FIFO queue is located on a semiconductor chip receiving and transmitting data in a computer system, typically a computer network. The FIFO queue has additional storage capability in the form of an expansion into the local memory of the computer system. The front and back ends of the FIFO, which are involved in receiving and transmitting data, are implemented on the chip. The FIFO expands into the space provided in the local memory only when the on-chip portion of the FIFO is full. The middle portion of the FIFO resides in expansion in the local memory. The local memory is accessed only in bursts of multiple credits, both for read transactions and for write transactions.
    Type: Grant
    Filed: June 20, 1997
    Date of Patent: June 20, 2000
    Assignee: Digital Equipment Corporation
    Inventors: Simoni Ben-Michael, Michael Ben-Nun, Yifat Ben-Shahar
  • Patent number: 6076059
    Abstract: In a computerized method, text segments of a text file are aligned with audio segments of an audio file. The text file includes written words, and the audio file includes spoken words. A vocabulary and language model are generated from the text segment. A word list is recognized from the audio segment using the vocabulary and language model. The word list is aligned with the text segment, and corresponding anchors are chosen in the word list and text segment. Using the anchors, the text segment and the audio segment are partitioned into unaligned and aligned segments according to the anchors. These steps are repeated for any unaligned segments until a termination condition is reached.
    Type: Grant
    Filed: August 29, 1997
    Date of Patent: June 13, 2000
    Assignee: Digital Equipment Corporation
    Inventors: Oren Glickman, Christopher Frank Joerg
  • Patent number: 6076129
    Abstract: A data bus sequencer for use by nodes coupled to a system bus for associating data transactions and address transactions on the bus. The data bus sequencer includes means for tracking address and command transactions occurring on an address bus, the means for tracking producing a sequence number tag corresponding to each address and command transaction occurring on the address bus. Means for associating data transactions with address and command transactions stores the sequence number tags corresponding to address and command transactions for which data transactions are to be initiated by the node. Further included are means for tracking data transactions occurring on a data bus, means for comparing tracked data transactions to associated data transactions, and means for initiating data transactions on the data bus in response to the comparison.
    Type: Grant
    Filed: June 6, 1997
    Date of Patent: June 13, 2000
    Assignee: Digital Equipment Corporation
    Inventors: David M. Fenwick, Denis J. Foley, Stephen R. Van Doren, David W. Hartwell, Elbert Bloom, Ricky C. Hetherington
  • Patent number: 6075704
    Abstract: In a modular tower building block system for containing computing system devices, an I/O bus is incorporated into the modular blocks of the building block system by using a printed circuit board to carry the I/O bus in each modular block. The printed circuit board is mounted and positioned in each modular block to electrically connect with a printed circuit board in a next adjacent modular block when two modular blocks are stacked on each other. Also, there are a plurality of I/O buses on the printed circuit boards and only one I/O bus is distributed from each modular block. The printed circuit board is precisely located in each modular block at a predetermined position. Alignment pins and receivers provide alignment between stacked modular blocks to precisely position one modular block to the other modular block. This also aligns electrical connectors on the printed circuit boards of the stacked blocks so that the connectors on the printed circuit boards from two blocks mate when the two blocks are stacked.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: June 13, 2000
    Assignee: Digital Equipment Corporation
    Inventors: Mark Frederick Amberg, Frank Michael Nemeth
  • Patent number: 6076158
    Abstract: A CPU of the RISC type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes limited to register-to-register operations and register load/store operations. Byte manipulation instructions include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream.
    Type: Grant
    Filed: July 1, 1993
    Date of Patent: June 13, 2000
    Assignee: Digital Equipment Corporation
    Inventors: Richard Lee Sites, Richard T. Witek
  • Patent number: 6076176
    Abstract: A technique for encoding failing bit addresses in a memory array with redundant portions such as column slices. The address or other identification of a column slice or other portion of a memory array is identified to test logic using a wired-OR bus configuration. The technique assigns a code consisting of predetermined number of asserted bits to each portion of the memory. If a failure condition is detected, the code associated with that portion is asserted onto the bus. Because the code for each memory portion always has a given number of asserted bits, a multi-bit failure situation can be distinguished from a single bit failure situation by counting the number of bits asserted.
    Type: Grant
    Filed: March 19, 1998
    Date of Patent: June 13, 2000
    Assignee: Digital Equipment Corporation
    Inventors: Donald A. Priore, Dilip K. Bhavsar, Tina P. Zou
  • Patent number: 6070009
    Abstract: A method is provided for estimating execution rates of program executions paths. The method samples path-identifying state information of selected instructions while executing the program in a processor. A control flow graph of the program is supplied, the control flow graph includes a plurality of path segments. The control flow graph is analyzed using the path-identifying state information to identify a set of path segments that are consistent with the sampled state information. The set of paths segments can be counted to determine their relative execution frequencies.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: May 30, 2000
    Assignee: Digital Equipment Corporation
    Inventors: Jeffrey Dean, Robert A. Eustace, James E. Hicks, Carl A. Waldspurger, William E. Weihl
  • Patent number: 6067543
    Abstract: A method for searching a plurality of index entries in an index of a database including parsing a query into one or more terms with an operator, generating a basic stream reader object to sequentially read the location of the index to determine a target location for the term, and generating a compound stream reader object to reference the plurality of basic stream reader objects associated with the term related by the operator to produce locations of words within a single record.
    Type: Grant
    Filed: August 18, 1998
    Date of Patent: May 23, 2000
    Assignee: Digital Equipment Corporation
    Inventor: Michael Burrows
  • Patent number: 6065033
    Abstract: An apparatus sums a plurality of columns of binary bits to produce a plurality of partial sum and carry bits. The bits of a particular column being of the same order of magnitude, and the bits of different columns differing in orders of magnitude. The apparatus includes one or more full adder. Each full adder receives three bits as an input to produce a first sum bit and a first carry bit as output. The apparatus also includes one or more half adders. Each half adder receives two bits as input to produce a second sum bit and a second carry bit as output. The full adders and half adder are interconnected as a plurality of interconnecting column adders. Each column adder sums bits of the input of at least one column and generates a partial sum and carry bit. Each column adder has a plurality of stages. A plurality of conductors interconnect the stages of each column adder with other stages in the same column adder and with stages in other adjacent column adders.
    Type: Grant
    Filed: February 28, 1997
    Date of Patent: May 16, 2000
    Assignee: Digital Equipment Corporation
    Inventor: Norman P. Jouppi
  • Patent number: 6061686
    Abstract: In response to a command by a local computer system, a copy of a remote document is downloaded onto a remote update network device from an origin network device. A predetermined time after the remote document copy is downloaded, the update network device interfaces with the origin network device to compare the remote document with the remote document copy. If the remote document has been modified since it was copied onto the update network device, the remote document copy is updated to reflect the modifications. When the local computer system reconnects to the network, the updated remote document copy may be downloaded into the memory of the local computer system if the remote document copy on the update network device is different than a local copy of the remote document stored in the local computer system.
    Type: Grant
    Filed: September 26, 1997
    Date of Patent: May 9, 2000
    Assignee: Digital Equipment Corporation
    Inventors: William Joseph Gauvin, Edward James Taranto
  • Patent number: 6061773
    Abstract: A virtual memory system includes a virtual address space including a process private space, a shared space, and a page table space located between the process private space and the shared space. The page table space includes page table entries mapping both the process private space and the shared space to physical memory. The page table entries might include a set of virtually contiguous process private page table entries adjacent to the process private space, and a set of virtually contiguous shared page table entries adjacent to the shared space. The process private space may include virtual addresses on a first side of a private/shared virtual address boundary, and the shared space includes virtual addresses on a second side of the private/shared virtual address boundary.
    Type: Grant
    Filed: May 3, 1996
    Date of Patent: May 9, 2000
    Assignee: Digital Equipment Corporation
    Inventors: Michael Seward Harvey, Karen Lee Noel
  • Patent number: 6052132
    Abstract: A technique for providing a computer generated face having coordinated eye and head movement is realized by providing a computer generated movable head and at least one computer generated movable eye. The movement of the computer generated movable head and the movement of the at least one computer generated movable eye are coordinated such that the movement of the computer generated movable head follows the movement of the at least one computer generated movable eye.
    Type: Grant
    Filed: February 6, 1998
    Date of Patent: April 18, 2000
    Assignee: Digital Equipment Corporation
    Inventors: Andrew Dean Christian, Brian Lyndall Avery, Keith Waters
  • Patent number: 6052706
    Abstract: In accordance with the present invention a circuit for performing an iterative process on a data stream is provided. The iterative process includes pipeline stages which operate on a portion of the data stream to produce an output which is an input to a succeeding stage. At least one of the pipeline stages includes a means for recirculating an output from the pipeline stage as an input to the pipeline stage for a predetermined number of times before passing the output to a succeeding stage. The predetermined number of times represents a clock period that includes more than one assertion of a clock signal. With such an arrangement, a circuit which performs a process, such as multiplication and division, in accordance with a particular bandwidth requirement requires less hardware than in other circuits performing the same process.
    Type: Grant
    Filed: November 25, 1997
    Date of Patent: April 18, 2000
    Assignee: Digital Equipment Corporation
    Inventors: William R. Wheeler, Matthew J. Adiletta
  • Patent number: 6049889
    Abstract: A multi-node computer network includes a plurality of nodes coupled together via a data link. Each of the nodes includes a local memory, which further comprises a shared memory. Certain items of data that are to be shared by the nodes are stored in the shared portion of memory. Associated with each of the shared data items is a data structure. When a node sharing data with other nodes in the system seeks to modify the data, it transmits the modifications over the data link to the other nodes in the network. Each update is received in order by each node in the cluster. As part of the last transmission by the modifying node, an acknowledgement request is sent to the receiving nodes in the cluster. Each node that receives the acknowledgment request returns an acknowledgement to the sending node. The returned acknowledgement is written to the data structure associated with the shared data item.
    Type: Grant
    Filed: January 13, 1998
    Date of Patent: April 11, 2000
    Assignee: Digital Equipment Corporation
    Inventors: Simon C. Steely, Jr., Glenn P. Garvey, Richard B. Gillett, Jr.
  • Patent number: 6047357
    Abstract: A cache memory system includes multiple cache levels arranged in a hierarchical fashion. A data item stored in a higher level cache level is also stored in all lower level caches. The most recent version of a data item is detected during an initial lookup of a higher level cache. The initial lookup of a higher level cache includes a comparison of address bits for the next lower level cache. Thus the most recent version of a data item is able to be detected without additional lookups to the lower level cache.
    Type: Grant
    Filed: January 27, 1995
    Date of Patent: April 4, 2000
    Assignee: Digital Equipment Corporation
    Inventors: Peter J. Bannon, Elizabeth M. Cooper
  • Patent number: 6047078
    Abstract: In a computerized method, a three-dimensional model is extracted from a sequence of images that includes a reference image. Each image in the sequence is registered with the reference image to determine image features. The image features are used to recover structure and motion parameters using geometric constraints in the form of a wireframe mode. A predicted appearance is generated for each image using the recovered structure and motion parameters, and each predicted appearance is registered with the corresponding image. The recovering, generating, and registering steps are repeated until the average pixel value difference (color or intensity) between the predicted appearances and the corresponding images is less than a predetermined threshold.
    Type: Grant
    Filed: October 3, 1997
    Date of Patent: April 4, 2000
    Assignee: Digital Equipment Corporation
    Inventor: Sing Bing Kang
  • Patent number: 6047286
    Abstract: A system for indexing information includes a memory and processor. The memory stores an index to information. The processor receives a first signal representing a query for a phrase corresponding to a concatenation of adjacent portions of the information. The processor processes the first signal so as to generate a second signal representing an entry for the phrase to be stored as part of the index in the memory.
    Type: Grant
    Filed: August 21, 1998
    Date of Patent: April 4, 2000
    Assignee: Digital Equipment Corporation
    Inventor: Michael Burrows
  • Patent number: 6043827
    Abstract: A technique for acknowledging multiple objects using a computer generated face is realized by determining the location of at least two objects relative to a display device. A computer generated face is produced on the display device, wherein the computer generated face has at least one eye. The at least one eye is alternately directed between the at least two objects.
    Type: Grant
    Filed: February 6, 1998
    Date of Patent: March 28, 2000
    Assignee: Digital Equipment Corporation
    Inventors: Andrew Dean Christian, Brian Lyndall Avery
  • Patent number: 6038576
    Abstract: A method for bit-depth increasing digital data represented by a first number of original bits which are sequentially ordered beginning with a start bit and ending with an end bit. To bit-depth increase the data, in an expanded presentation, the original bits are replicated in the sequential order starting with the start bit to form replication bits. The original bits are appended with a second number of the replication bits to form the expanded presentation of the digital data. The appended replication bits start with the start bit and are in the sequential order of the original bits.
    Type: Grant
    Filed: December 2, 1997
    Date of Patent: March 14, 2000
    Assignee: Digital Equipment Corporation
    Inventors: Robert A. Ulichney, Shiufun Cheung
  • Patent number: 6038689
    Abstract: A fault notification system detects the non-operational state of the computer, or other type of network device, and transmits network messages from the device to a monitoring system or control console in the case of a detected non-operational state. The network messages are constructed by the network device when it is operational, preferably by the operating system before any problem is detected. This message is then stored in some non-volatile storage medium, such as the BIOS memory in one embodiment. As a result, very limited operating system functionality must be replicated in the device BIOS. Only the actual transmitted message must be stored and the commands necessary to have the message sent. In some embodiments, an auxiliary processor is used to detect improper operation, preferably via a dedicated, secondary bus. It loads the relevant messages into the transport buffer for transmission to the monitoring system even where the computer's CPU may not be operational.
    Type: Grant
    Filed: August 21, 1997
    Date of Patent: March 14, 2000
    Assignee: Digital Equipment Corporation
    Inventors: Thomas J. Schmidt, Lawrence Huppert