Abstract: A set of conductive plates are positioned adjacent to and in close proximity with a unidirectional heatsink on a high frequency integrated circuit. The set of plates is generally electrically attached to the same ground potential voltage supply as the integrated circuit and serves to damped unwanted radio frequency electromagnetic radiation normally emitted by heatsinks. The same arrangement of plates can also serve as an external electromagnetic interference shield apparatus for the integrated circuit. The plates may alternatively be comprised of a conductive mesh to allow air flow through the plates.

Abstract: An apparatus for displaying documents on a computer controlled display device provides a method for clipping. To clip a document is to restrict the viewable area of the screen object on the computer controlled display device associated with the document. A workspace viewer process maintains the documents in a three-dimensional virtual workspace. A document renderer and attribute-value pairs accomplish clipping in the virtual workspace. Clip stops constrain the clipping edges of a document so that the document may be clipped only to a specified set of positions.

Abstract: A memory controller for optimizing direct memory access (DMA) read transactions wherein a number of cache lines are prefetched from a main memory as specified in a prefetch length field stored in a page table. When all prefetch data has been fetched, the memory controller waits to determine whether the initiator of the DMA read transaction will request additional data. If additional data is needed, additional cache lines are fetched. Once the initiator terminates the DMA read transaction, the prefetch length field for a selected page other entry in the table is updated to reflect the actual DMA read transaction length. As a result, an optimum number of cache lines are always prefetched thereby reducing the number of wait states required.

Abstract: A document management apparatus provides a user to define delimiters in order to specify portions of documents or attributes of documents to be retrieved from a document repository. The repository is searched for the defined delimiters and the portions of the documents or the attributes of documents are retrieved and put into a cache memory. The user-defined delimiters may be multi-character delimiters. The cache memory and the document repository may be connected over a network.

Abstract: A multiprocessor having improved bus efficiency is shown to include a number of processing units and a memory coupled to a system bus. Also coupled to the system bus are at least one I/O bridge systems. A method for improving partial cache line writes from I/O devices to the central processing units incorporates cache coherency protocol and an enhanced invalidation scheme to ensure atomicity which minimizing the bus utilization. In addition, a method for allowing peer-to-peer communication between I/O devices coupled to the system bus via different I/O bridges includes a command and address space configuration that allows for communication without the involvement of any central processing device. Interrupt performance is improved through the storage of an interrupt data structure in main memory. The I/O bridges maintain the data structure, and when the CPU is available the interrupts can be accessed by a fast memory read; thereby reducing the requirement of I/O reads for interrupt handling.

Abstract: A boot strap assignment system is disclosed for a symmetric multiprocessor computer in which the role of the boot strap processor is assigned to one of the working processors by a central agent as part of power-on configuration. The system includes a system management processor which monitors the operation of the multiprocessor computer and controls a switching circuit that selectively transmits the boot strap assignment signal from the central agent to the working processors. Since the management processor monitors environmental conditions and shut-down events, it can predict the failure of working processors and assign the bootstrapping function appropriately. A watch dog timer is also provided in case the bootstrapping fails so that another working processor can be assigned the task of booting up the computer.

Abstract: A computer implemented method detects concurrency errors in programs. Machine executable images of multiple program threads are instrumented to locate and replace instructions which affect concurrency states of the threads. Concurrency state information is recorded in a memory while the multiple threads are executing. The recorded concurrency state information is analyzed, and inconsistent dynamic concurrency state transitions are reported as concurrency errors.

Abstract: In a computerized method, performance data collected while a computer system executed instructions of a program are analyzed. The method collects performance data while executing the program. The performance data includes sample counts of instructions executed. The program is analyzed to determine classes of instructions. Instructions of the same equivalence class all execute the identical number of times. The execution frequencies for each instructions of each equivalence class is estimated. The estimated execution frequencies can then be used to determine the average number of cycles required to issue each instruction of each equivalence class. The average number of cycles can be compared with the minimum number of cycles to determine the number of dynamic stall cycles incurred by the instructions. Furthermore, reasons for the dynamic stall cycles can be inferred.

Abstract: A hands-free navigation system for tracking a head and responsively adjusting the display of a virtual reality environment includes a camera, the camera employed to follow movements of the head, a computer system connected to the camera, the computer system including a memory, a central processing unit (CPU), a digitizer, the digitizer providing a current image of a face of the head, a face tracker, the face tracker including the capability of receiving a reference face image from the digitizer, of receiving the current face image from the digitizer, of determining a head translation and orientation, and of providing the head translation and orientation to a three dimensional virtual environment viewer connected to the computer system for display of the virtual environment at the desired viewpoint.

Abstract: A computer implemented method for down-loading mail messages in a distributed computer system. The distributed mail service system includes a plurality of client computers connected to a mail service system via a network. Mail messages are stored in message files of the mail service system, a particular mail message includes a primary component encoded in a first format, and at least one secondary component encoded in a second format different than the first component. The particular mail message is requested by a particular one of the plurality of client computer systems. The secondary component is replaced with a hot-link. The primary component and the hot-link are sent to the particular client computer.

Abstract: A technique for implementing a programmable thermal model of an integrated circuit component such as a central processing unit (CPU) and its associated heat sink. The model estimates the die temperature of the component as if there were no cooling devices present in the system such as a forced air cooling fan by integrating the thermal energy added when the component is active and by integrating the thermal energy removed when it is idle. A programmable power value may be used to represent the heat added to the model at each model sample period. The effect of a heat sink in cooling the idle component may be modeled by reducing the value of the heat accumulator by a predetermined fractional amount during each sample period. The decay time constant for the model may be changed by then adjusting the sample period.

Abstract: A portable computer and docking station combination, comprising first and second batteries and first and second battery charging circuit portions, with automatic sequencing of charging between the batteries. The system includes means for charging a first battery based on an amount of current flowing into the computer circuitry, and means for charging a second battery based on an amount of current flowing into the first battery and into the computer circuitry.

Abstract: In a computer implemented method, a list of variable size integers is encoded in a memory. Each variable size integer is expressed as a set of a minimum number of bytes. A fixed number the bytes of the sets are grouped with an associated bit map into a logical memory word unit. Each bit map has one continuation bit for each of the fixed number of bytes. Each continuation bit indicating whether or not a particular variable size integer continues into a following byte. An entry is stored in an array for each possible pattern of continuation bits of the bit maps. Each entry including a plurality of fields. There is one field for each of the fixed number of bytes in each group. Each field stories a length of a corresponding set of bytes expressing a particular variable size integer in the group. The entries provide a decoding table that is indexable by the bit maps to recover the list of variable size integers.

Abstract: A singulated die test socket is presented. The socket allows for die to be fully functional tested and thermal tested before packaging. The socket is created from similar silicon material as the die being tested thereby producing a match of thermal coefficients of expansion between the socket and the die. It is also possible to provide additional circuitry in the socket to aid in the testing of the die. The test socket may also be used as an integrated circuit package by adding a lid, used to seal the die within the package cavity. In both uses the socket cavity may be created with sloping sidewalls, the sloping sidewalls providing for self alignment of the die within socket cavity.

Abstract: A computer system is directed to convert a program written as a plurality of high level source code modules into corresponding machine executable code. The source code modules are compiled into an object code module, and the object code modules are translated into a single linked code module in the form of a register translation language and logical symbol table compatible with a plurality of computer system hardware architectures. The source code program structures are recovered from the linked code module, and the linked code module is partitioned into a plurality of procedure, and instructions of each of the procedures grouped into basic blocks. A procedure flow graph is constructed for each of the procedures, and a program call graph is constructed for the linked code module. The linked code module is modified by eliminating dead code and moving loop-invariant code from loops.

Abstract: An apparatus is provided for sampling instructions in a processor pipeline of a system. The pipeline has a plurality of processing stages. The apparatus includes a fetch unit for fetching instructions into a first stage of the pipeline. Certain randomly selected instructions are identified, and state information of the system is sampled while a particular selected instruction is in any stage of the pipeline. Software is informed when the particular selected instruction leaves the pipeline so that the software can read any of the sampled state information.

Abstract: A computer system for executing a binary image conversion system which converts instructions from a instruction set of a first, non native computer system to a second, different, native computer system, includes an run-time system which in response to a non-native image of an application program written for a non-native instruction set provides an native instruction or a native instruction routine. The run-time system collects profile data in response to execution of the native instructions to determine execution characteristics of the non-native instruction. Thereafter, the non-native instructions and the profile statistics are fed to a binary translator operating in a background mode and which is responsive to the profile data generated by the run-time system to form a translated native image. The run-time system and the binary translator are under the control of a server process.

Abstract: A low static enclosure has an interior for holding an electronic device therein. The electronic device has opposing walls each having a guide rail thereon. The enclosure has a bottom, a top, and a backplane between the bottom and top at their respective back edges. The backplane has an electric connector on its interior surface. The bottom and top each have a flat continuous interior facing surface with a groove extending from the front edge to the back edge. The grooves on the bottom and top are for cooperation with the guide rails on the opposing walls of the electronic device to slide the electronic device along the bottom and top respectively so that an electric connector on the electronic device mates with the electric connector on the interior surface of the backplane. The flat continuous interior facing surfaces of the bottom and top discourage ESD between the surfaces and the electronic device.

Abstract: An apparatus and method a method for performing two-pass real time video compression is provided. Tactical decisions such as encoding and quantization values are determined in software, whereas functional execution steps are performed in hardware. By appropriately apportioning the tasks between software and hardware, the benefits of each type of processing are exploited, while minimizing both hardware complexity and data transfer requirements. One key concept that allows the compression unit to operate in real time is that the architecture and pipelining both allow for B frames to be executed out of order. By buffering B frames, two-pass motion estimation techniques can be performed to tailor bit usage to the requirements of the frame, and thereby provide a more appealing output image.

Abstract: A method and apparatus for reclaiming a page of physical memory in a computer system for subsequent mappings to a virtual address is provided in a system wherein the physical memory is apportioned into a number of pages. The computer system includes a temporary storage device, such as a cache, for storing a subset of the pages in memory. Each of the pages stored in the cache are accessed using a cache page address. Virtual addresses are mapped to physical addresses responsive to monitoring use of the cache page addresses associated with the allocated physical addresses. According to the present invention, a page of physical memory is reclaimed such that a substantially even distribution of cache page addresses is maintained in physical addresses of both mapped and available pages of memory. Pages are originally placed on the clean list in response to characteristics of each page including the cache page address of the page.