Abstract: A computer implemented method performs constrained searching of an index of a database. The information of the database is stored as a plurality of records. A unique location is assigned to each indexable portion of information of the database. Index entries are written to a memory where each index entry includes a word entry representing a unique indexable portion of information, and one or more location entries for each occurrence of the unique indexable portion information. The index entries are sorted according to a collating order of the word entries, and sequentially according to the location entries of each index entry. A query is parsed to generate a first term and a second term related by an AND logical operator, the AND operator requires that a first index entry corresponding to the first term and a second index entry corresponding to the second term both have locations in the same record to satisfy a query.

Abstract: A new pseudo network adapter is disclosed providing an interface for capturing packets from a local communications protocol stack for transmission on the virtual private network. The system further includes a Dynamic Host Configuration Protocol (DHCP) server emulator, and an Address Resolution Protocol (ARP) server emulator. The new system indicates to the local communications protocol stack that nodes on a remote private network are reachable through a gateway that is in turn reachable through the pseudo network adapter. The new pseudo network adapter includes a transmit path for processing data packets from the local communications protocol stack for transmission through the pseudo network adapter. The transmit path includes an encryption engine for encrypting the data packets and an encapsulation engine for encapsulating the encrypted data packets into tunnel data frames.

Abstract: A pipelined floating point processor including an add pipe for performing floating point additions is described. The add pipe includes a circuit to predict a normalization shift amount from examination of input operands, a circuit to determine the "Sticky bit" from the input operands, and a rounding adder which adds a pair of operands and rounds the result in a single pipeline stage operation. The rounding adder incorporates effects due to rounding in select logic for a series of carry select adders. The adder also aligns the datapath to permit economical storage and retrieval of floating point and integer operands for floating point or conversions operations. The floating point processor also includes in the adder pipeline a divider circuit include a quotient register having overflow quotient bit positions to detect the end of a division operation.

Abstract: In a computerized method, a set of radial distortion parameters are recovered from a single image by selecting arbitrarily oriented straight lines in a single image using an input device. Then, objective functions in Cartesian form are minimized using a least-squares fit formulation to recover the set of radial distortion parameters.

Abstract: A semi-mobile desktop personal computer incorporating the features of a desktop personal computer with the mobility of a mobile personal computer. The computer includes a system enclosure attached to a storage enclosure, the storage enclosure extends outside the system enclosure and provides stability for the system enclosure by engaging the surface on which the system enclosure has been placed for use.

Abstract: A client-server network including a number of client computer systems, each of the client computer systems having a network interface, a number of server computer systems, each of the server computer systems having a network interface, and a replicator system connecting the client computer systems to the server computer systems, the replicator system transparently processing a number of requests from the client systems to a number of services resident in the server systems.

Abstract: A method and apparatus for performing error detection in a network is disclosed. An error counter is stored in a common memory location accessible by all nodes. The error counter includes separate partitions associated with each node in the network. Each partition includes two error counter values representing, respectively, sending and transmission error counts, for a corresponding node. No global locking mechanism is required to synchronize access to the commonly accessed error counter. Rather, access to the error counter is provided by having code executing on each node adhering to rules regarding the types of access to the various partitions in the error counter. Each node may read from any partition, but may only write to its own partition.

Abstract: In a method for scheduling instructions executed in a computer system including a processor and a memory subsystem, pipeline latencies and resource utilization are measured by sampling hardware while the instructions are executing. The instructions are then scheduled according to the measured latencies and resource utilizations using an instruction scheduler.

Abstract: A computer system for executing a binary image conversion system which converts instructions from a instruction set of a first, non native computer system to a second, different native computer system, includes an run-time system which in response to a non-native image of an application program written for a non-native instruction set provides an native instruction or a native instruction routine. The run-time system collects profile data in response to execution of the native instructions to determine execution characteristics of the non-native instruction. Thereafter, the non-native instructions and the profile statistics are fed to a binary translator operating in a background mode and which is responsive to the profile data generated by the run-time system to form a translated native image. The run-time system and the binary translator are under the control of a server process.

Abstract: A computer implemented method for filtering mail messages in a distributed computer system. The distributed mail service system includes a plurality of client computers connected to a mail service system via a network. Mail messages are stored in message files of the mail service system. Each mail message is parsed and indexed to generate a full-text index of the mail service system. A query is composed, the query includes terms and operators. The query is stored in the mail service system as a named filter query. A new mail message received by the mail service system is parsed, indexed and searched to determine if the content of the new mail message does not match on the named filter query, in which case an inbox label and an unread label to the new mail message.

Abstract: A technique reduces the latency of a memory barrier (MB) operation used to impose an inter-reference order between sets of memory reference operations issued by a processor to a multiprocessor system having a shared memory. The technique comprises issuing the MB operation immediately after issuing a first set of memory reference operations (i.e., the pre-MB operations) without waiting for responses to those pre-MB operations. Issuance of the MB operation to the system results in serialization of that operation and generation of a MB Acknowledgment (MB-Ack) command. The MB-Ack is loaded into a probe queue of the issuing processor and, according to the invention, functions to pull-in all previously ordered invalidate and probe commands in that queue. By ensuring that the probes and invalidates are ordered before the MB-Ack is received at the issuing processor, the inventive technique provides the appearance that all pre-MB references have completed.

Abstract: A cache includes an address cache for storing memory addresses. An address queue is connected to the address cache for storing missed addresses in the order that the address cache is probed. A memory controller receives the missed addresses from the address queue. A data queue receives data stored at the missed addresses from the memory controller. A probe result queue is connected to the address cache for storing data cache line addresses and hit/miss information. A multiplexer connected to the data cache, the data queue, and the probe result queue selects output data from the data cache or the data queue depending on the hit/miss information.

Abstract: A method of managing computer memory pages. The sharing of a program-accessible page between two processes is managed by a predefined mechanism of a memory manager. The sharing of a page table page between the processes is managed by the same predefined mechanism. The data structures used by the mechanism are equally applicable to sharing program-accessible pages or page table pages.

Abstract: A high-speed CMOS latch includes at each storage node a pull-up P-transistor with its gate tied to a dynamic node, and a pull-down N-transistor with its gate controlled by the inverse of the states of the remaining dynamic nodes. The P-transistor drives the storage node high to VDD, and the N-transistor drives the node low to VSS, as appropriate. During evaluation, one dynamic node discharges to a low state and in response each storage node is driven relatively quickly to the desired high or low state through either the associated pull-up or pull-down transistor. Precharging P-transistors drive the dynamic nodes high during precharge periods. As the dynamic nodes go high, they turn off all of the pull-up and pull-down transistors that drive the latch storage nodes, and the latch retains the evaluated state of the dynamic nodes until the start of the next evaluation cycle. Accordingly, the latch does not require a separate clock.

Abstract: Using an input device of a computer system, a graphic drawing is defined to include at least one graphic component. The graphic component is subject to a plurality of constraints. At least one of the constraints is redundant with respect to the other constraints. Approximate linear equations are substituted for the constraints. A subset of the equations are selected to determine a converging solution for the redundantly constrained graphic drawing.

Abstract: A method of encoding a message including a plurality of data items, includes identifying maximum and minimum numbers of first edges to be associated with data items. A first distribution of different numbers of first edges, ranging from the maximum to the minimum number of first edges, to be associated with the data items is computed. A first associated number of first edges, within the range, is established for each data item, the different numbers of first edges being associated with the data items according to the computed first distribution. A maximum and minimum number of second edges to be associated with redundant data items are identified. A second distribution of numbers of second edges, ranging from the maximum to the minimum number of second edges, to be associated with the redundant data items is computed.

Abstract: A circuit which protects an integrated circuit (IC) device from damage due to electrostatic discharge (ESD). The protection circuit includes an N-channel metal oxide semiconductor field effect transistor (MOSFET) clamping device and a gate modulation circuit. The source and drain of the MOSFET clamp are connected between an input/output (I/O) pad of the IC and a ground reference voltage. During normal operation of the IC, the gate modulation circuit disables the MOSFET clamp by connecting its gate terminal to a ground reference voltage. This permits signal voltages to pass between the I/O pad and any operating circuits connected to the pad. During an ESD event, the gate modulation circuit connects the gate to the I/O pad, which enables the MOSFET clamp, causing any ESD voltages and resulting currents to be shunted through the MOSFET clamp to ground. As a result, the ESD clamp reaches its clamped-to snapback voltage via an increase in MOSFET channel current, and not via junction breakdown.

Abstract: A computer implemented method provides access to processes and data using strengthened password. During an initialization phase, an access code is stored in a memory of a computer system. The access code is an application of a one-way hash function to a concatenation of a password and a password supplement. The size of the password supplement is a fixed number of bits. During operation of the system, a user enters a password, and the one-way hash function is applied to concatenations of the password and possible values having the size of the password supplement to yield trial access codes. Access is granted when one of the trial access codes is identical to the stored access code.

Abstract: In a computerized method for predicting a particular user preference for an item based on observations made about the item by other users, client computers are used to enter the observations about the items. The observations are forwarded to a server computer via a network. The observations are collected in a database of the server computer. Using factor analysis, a solver module of the server computer analyzes the observations to generate a model of the observations. The models are distributed to the client computers via the network. The client computer makes predictions of preferences of the particular user using the models.

Abstract: A relatively small FIFO queue is located on a semiconductor chip receiving and transmitting data in a computer system, typically a computer network. The FIFO queue has additional storage capability in the form of an expansion into the local memory of the computer system. The front and back ends of the FIFO, which are involved in receiving and transmitting data, are implemented on the chip. The FIFO expands into the space provided in the local memory only when the on-chip portion of the FIFO is full. The middle portion of the FIFO resides in expansion in the local memory. The local memory is accessed only in bursts of multiple credits, both for read transactions and for write transactions.