Abstract: A new class of general purpose computers called Programmable Reduced Instruction Set Computers (PRISC) use RISC techniques a basis for operation. In addition to the conventional RISC instructions, PRISC computers provide hardware programmable resources which can be configured optimally for a given user application. A given user application is compiled using a PRISC compiler which recognizes and evaluates complex instructions into a Boolean expression which is assigned an identifier and stored in conventional memory. The recognition of instructions which may be programmed in hardware is achieved through a combination of bit width analysis and instruction optimization. During execution of the user application on the PRISC computer, the stored expressions are loaded as needed into a programmable functional unit. Once loaded, the expressions are executed during a single instruction cycle.

Abstract: In order to provide a thermal coupling between a heat source and a heat sink, an integrated interleaved-fin connector is provided. A first substrate includes a first side surface and a second side surface. A plurality of heat generating devices are formed in the first side surface. A plurality of first channels are etched in the second side surface to form a plurality of first fins. A second substrate has a plurality of second channels etched therein to form a plurality of second fins and a base. The base is for thermally engaging with a heat sink. The first and second fins providing a thermally conductive path from the heat generating devices to the heat sink when interleaved with each other.

Abstract: A method for mapping a digitized image of a face on to a reference wireframe topology in a computer system is provided, the image composed of pixels, the wireframe composed of interconnected nodes, the method including the steps of determining facial features from the pixels, determining facial landmark points from the facial features, computing displacements for each one of the interconnected nodes, and manually finetuning the displacements in response to the step of computing.

Abstract: A table of web pages is maintained by requesting a web page, receiving the requested web page, and identifying an address, such as a URL, of the received web page. A locator, such as a fingerprint, which represents the address of the received web page is entered into the table of web pages to maintain the table. The locator has a size smaller than the address.

Abstract: In a computerized method for labeling data records, data records are received in an index server. The records are parsed into words, and the words are stored in a full-text index. Labels are added to the data records and the full-text index. The data records are accessed by searching the full-text index using queries including the words and the labels of the data records. Labels can be removed from the full-text index.

Abstract: A semiconductor structure having: semiconductor devices formed in an inner region of a semiconductor chip; a seal ring formed in the chip and disposed about the inner region; and, a plurality of trenches formed along a surface of the chip. The trenches are disposed in a corner region of the chip. A portion of the seal ring is disposed between the trenches and the inner region of the chip. The trenches are disposed along axes oblique to outer edges of the chip. A method is provided for encapsulating a semiconductor chip. The method includes the steps of: providing a semiconductor chip having active semiconductor devices in an inner region of the semiconductor chip and a seal ring in the chip about the inner region; and, forming a plurality of trenches in the chip, a portion of the seal ring being formed between the trenches and the inner region of the chip. A cover is formed having bottom portions in the trenches and on the passivation layer.

Abstract: A method for generating synthetic speech uses detection of natural timing boundaries in words to be spoken by the synthetic speech system, to produce natural timing intervals. Phonemes are identified in the natural timing intervals. Time durations are assigned for each of the phonemes. A time duration of a selected phoneme is changed to achieve a desired time duration for a selected natural timing interval containing the phoneme. The natural timing interval may be selected to be a syllable. The natural timing interval may be selected to be the interval between two stressed phonemes. The natural timing intervals may be set to substantially the same duration between timing boundaries by changing the phoneme durations in accordance with rhythm of the language of synthesized speech. Durations of preselected phonemes, however, may remain unchanged.

Abstract: A variable precedence priority encoder apparatus is provided having a plurality of inputs, each receiving a corresponding bit of an input vector, and a like plurality of outputs. Each output is associated with a corresponding one of the plurality of inputs, thereby forming a plurality of input/output pairs. The encoder circuit also includes a priority assignment circuit coupling each input of the plurality of inputs to its associated corresponding output of the plurality of outputs. The priority assignment circuit assigns a priority to each input/output pair, such that an output, which corresponds to an input which receives an asserted bit, and which has a highest priority, provides an asserted bit while all other outputs provide bits that are not asserted. The priority assigned to each input can be dynamically updated within the priority assignment circuit. Updates of priority that shift the priority position by one or more inputs can be done all using the same circuit.

Abstract: A delay circuit comprises a tapped delay element line constructed from delay elements with fixed delay intervals and a multiplexer for selecting the signal at one of the taps to produce a variable delay through the circuit. The multiplexer is controlled by a selection circuit which receives an input indicative of the actual delay time through the delay circuit from an oscillator constructed from the same fixed delay elements as the delay line.

Abstract: A method and apparatus for dynamically updating virtual to physical address mappings in order to reduce cache thrashing is disclosed in an example computer system having a memory apportioned into a number of pages. A cache is included in the computer system to store a subset of the pages of memory. Each of the pages of memory is addressed by a physical address that includes a cache page address portion. The pages of cache memory are accessed using a cache page address, which corresponds to the cache page address portion of the physical address of a corresponding page of memory. The disclosed system monitors the activity of virtual addresses and uses the activity of virtual addresses to increment cache page address activity counters. The cache page address activity counters are monitored to identify those cache page addresses that are frequently being accessed within a process to identify potential performance problems, such as thrashing.

Abstract: A method and apparatus is presented for video image compression using a unique operand decomposition technique combined with an innovative data scatter and retrieve process. This combination of features allows the use of single ported RAM structures where multiported RAMS would normally be used, such as when retrieving two operands in the same time cycle. As applied to the Discrete Cosine Transformation this method and apparatus additionally allows elimination of the usual prior art use of a separate transpose matrix buffer. The elimination of the separate transpose matrix buffer is accomplished by combining the transpose matrix intermediate results memory storage with the memory buffer used for the other intermediate results in a double buffer system.

Abstract: A system for indexing stored information includes a processor and memory. The processor parses the information into indexable words. Each word represents either a portion of the information or an attribute of one or more portions of the information. The memory stores index entries. Each index entry includes a word entry representing a unique one of the words, and one or more location entries indicating a location of the unique word within the information.

Abstract: If the exponents of a floating-point-processor addition pipeline's input operands are equal, a signal (INVERT) that determines whether the pipeline's sole full-width carry-propagate mantissa adder (34) will invert one of its inputs results from an inversion-determination circuit (FIG. 11) that determines whether the sole set bit in a decoded normalization-shift signal (NORM.sub.-- SHIFT) occupies the same position as a set bit in a signal (FRAC.sub.-- A.sub.-- GT.sub.-- B) representing what the possible normalization amounts will be if a first of the mantissas is greater than the other, second mantissa. Consequently, a bit-comparison operation (56) that employs no full-width carry-propagate addition can determine the amount of normalization shifting to be performed by bit shifters (30 and 32) disposed in respective processing trains that generate mantissa inputs to the mantissa adder (34).

Abstract: Multicast addresses on a computer network are dynamically assigned to a temporary node task. In particular, a server dynamically assigns a multicast address to a data stream in response to a request for the data stream from a client. The server assigns the multicast address in cooperation with other servers from a pool of network-allocated but unassigned multicast addresses. Once the data stream is terminated, the assigned multicast address is deassigned and returned to the pool of unassigned multicast addresses for possible reuse by the nodes.

Abstract: A computer implemented method for generating a compressed index of information. The information is stored as a plurality of records in a database. Indexable portions of information are sequentially parsed to generate words and metawords. The words represent the portions, and the metawords represent attributes of the portions. A location is sequentially assigned to each word and metaword in the order that the portions are parsed to form pairs. The pairs are sorted first according to the words and metawords, and second according to the locations. Index entries are written to a memory for each unique word and metaword. Each index entry includes a word entry or a metaword entry, and one or more location entries. The word and metaword entries use a prefix encoding which indicates the number of bytes that the unique word or metaword of a next index entry has in common with the unique word or metaword of a previous index entry. The location entries use a delta value encoding.

Abstract: Techniques used in program development using a grammar sensitive editor are described. Input within an edit buffer is processed by a lexical and syntax analyzer in response to various syntactic and lexical states. Actions such as updating various multimedia indices are performed. Users are guided through program development through prompts for menu selection. The items transmitted on the menu are in accordance with the current state of lexical and syntactic processing. If an input in the edit buffer is invalid, the erroneous text is detected via the lexical and syntax analyzers and the erroneous text is highlighted. Additionally, transmitted via the menu is a selection of correct and valid alternatives from which the user may select to be included in the edit buffer.

Abstract: A method for mapping a digitized image of a face to a wireframe is provided. The wireframe is composed of a plurality of nodes connected by lines. The method includes the steps of detecting a plurality of facial features from the plurality of pixels of a reference facial image. Corresponding facial landmark nodes in the wireframe topology are determined. A transform between the facial features and the landmark nodes is computed to map the wireframe topology to reference facial image. The reference facial image and a target facial image are cropped using a bounding box. The cropped reference facial image is registered with the cropped target facial image to determine a displacement field. The displacement field is applied to the mapped wireframe topology for the reference facial image to map the target facial image to the wireframe topology.

Abstract: In a computer system, a data structure is provided in memory for storing one or more data files from an external device. The data files stored in the data structure are accessible by a number of processes executing in the computer system. The computer system includes a storage device such as a cache for storing data from a subset of pages of the memory. Each of the pages of the cache is referred to as a cache page, having an associated cache page address. A physical address is allocated for storing each page of a retrieved data file stored in the data structure such that a cache page address portion of the physical address is selected from the available cache page addresses. The physical address is further selected such that the cache page addresses are substantially evenly distributed amongst the pages of the retrieved data file and the data structure in order to minimize thrashing in the cache and enhance performance.

Abstract: An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory.

Abstract: An optical transceiver for transceiving optical signals in an optical LAN includes a first transceiver that detects and transmits the optical signals, a second transceiver that detects and transmits the optical signals, a control coupled to the first and second transceivers, the control transferring information carried by the optical signals between the transceivers, a power storage coupled to the control, and to the transceivers, and a photovoltaic cell coupled to the power storage for replenishing its power.