Abstract: A flash memory device includes a source region formed in an active region of a semiconductor substrate; a recessed region formed in the active region on either side of the source region, the recessed region including a recess surface having sidewalls; floating gates formed at the sidewalls of the recess surface by interposing a tunnel insulating film; a source line formed on the source region across the active region; and control gate electrodes formed at sidewalls of the source line across a portion of the active region where the floating gates are formed. The floating gates and the control gate electrodes are formed by anisotropically etching a conformal conductive film to have a spacer structure. Cell transistor size can be reduced by forming a deposition gate structure at both sides of the source line, and short channel effects can be minimized by forming the channel between the sidewalls of a recess surface.

Abstract: A method for manufacturing a semiconductor device includes forming a gate insulating layer, a gate and a protective layer on a semiconductor substrate, forming a spacer on lateral sides of the protective layer and the gate, forming one or more junction regions in the semiconductor substrate at sides of the gate, partially filling a gap between adjacent gates by selectively forming a conductive layer on an exposed portion of the semiconductor substrate between the adjacent gates, forming an insulating layer over the semiconductor substrate so as to fill a full height of the gap between the adjacent gates, and forming a contact hole partially exposing the conductive layer by etching the insulating layer.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate in which a first interlayer insulation layer having a first via hole and a first trench is formed. The semiconductor device also includes a first via plug and a first metal line respectively formed by filling the first via hole and the first trench with a first metal, a predetermined scratch being formed on the first metal line; and a second via plug a second metal line respectively formed by filling a second via hole and a second trench with a second metal, the second metal lines being separated.

Abstract: Disclosed is a static random access memory (SRAM), which includes first and second access transistors composed of metal oxide semiconductor (MOS) transistors, first and second drive transistors composed of MOS transistors, and first and second p-channel thin film transistors (TFTs) used as pull-up devices. The SRAM includes a ground potential layer disposed as a common source of the first and second drive transistors, and formed by implanting a dopant into a semiconductor substrate, a power supply potential layer connected with sources of the first and second p-channel TFTs, and an insulating layer formed on the substrate and interposed between the ground potential layer and the power supply potential layer.

Abstract: The present disclosure provides an exposure method for a semiconductor device, in which whether a specific pattern corresponds to a sparse area or a dense area is decided to employ a specific phase-shift mask and by which critical dimension uniformity and resolution of the pattern are enhanced. One example method includes defining a hole area for a plurality of holes into a dense area and a sparse area, coating a photoresist layer on a substrate having a plurality of elements formed thereon, carrying out a first exposure on the photoresist layer using a first photomask having patterns corresponding to the dense and sparse areas, respectively, and carrying out a second exposure on the photoresist layer using a second photomask having at least two halftone layers provided to portions corresponding to the dense and sparse areas, respectively wherein the at least two halftone layers differ from each other in transmitivity, respectively.

Abstract: Provided is a LDMOS device and method for manufacturing. The LDMOS device includes a second conductive type buried layer formed in a first conductive type substrate. A first conductive type first well is formed in the buried layer and a field insulator with a gate insulating layer at both sides are formed on the first well. On one side of the field insulator is formed a first conductive type second well and a source region formed therein. On the other side of the field insulator is formed an isolated drain region. A gate electrode is formed on the gate insulating layer on the source region and a first field plate is formed on a portion of the field insulator and connected with the gate electrode. A second field plate is formed on another portion of the field insulator and spaced apart from the first field plate.

Abstract: Provided are a CMOS image sensor in which microlenses are formed in a remaining space in a patterned light shielding layer to improve image sensor characteristics and to protect the microlenses during packaging. The CMOS image sensor may include: a semiconductor substrate; at least one photodiode on or in the semiconductor substrate; a first insulating layer on the substrate including the photodiode(s); a plurality of metal lines on and/or in the first insulating layer; a second insulating layer on the first insulating layer including at least some of the metal lines; a patterned light shielding layer on the second insulating layer; and microlenses in a remaining space on the second insulating layer.

Abstract: A nonvolatile (e.g., flash) memory device includes a substrate having a plurality of isolation areas and active areas; a trench formed on the isolation area; a first electrode layer formed on an inner wall of the trench; a first gate oxide layer formed between the inner wall of the trench and the first electrode layer; a junction area formed on the active area; a second gate oxide layer formed on the entire surface of the substrate including the first electrode layer, the first gate oxide layer, the trench and the junction area; a tunnel oxide layer formed on a part of the second gate oxide layer corresponding to the active area; and a second electrode layer formed on the active area and in the trench.

Abstract: Disclosed are a CMOS image sensor and a manufacturing method thereof.

Abstract: A high voltage BICMOS device and a method for manufacturing the same, which may improve the reliability of the device by securing a distance between adjacent DUF regions, are provided. The high voltage BICMOS device includes: a reverse diffusion under field (DUF) region formed by patterning a predetermined region of a semiconductor substrate; a diffusion under field (DUF) region formed in the substrate adjacent to the reverse DUF region; a spacer formed at a sidewall of the reverse DUF region; an epitaxial layer formed on an entire surface of the substrate; and a well region formed in contact with the DUF region.

Abstract: A method of forming an aluminum line of a semiconductor device where first A metal thin layer, a first aluminum layer, and a first B metal thin layer are sequentially applied on an interlayer insulating layer. A photolithography process is performed to form a metal line pattern, and etching is performed thereon. An intermetallic dielectric layer is applied on the metal line pattern. The first B metal thin layer is removed by a chemical mechanical planarization process to form a first stage metal line. A second aluminum layer and a second metal thin layer are sequentially applied. Photoresist is applied, a photolithography process is performed to form a metal line pattern, and etching is performed to form a second stage metal line. An intermetallic dielectric layer is applied on the second stage metal line. A chemical mechanical planarization process is performed on the second intermetallic dielectric layer.

Abstract: A method of manufacturing a semiconductor device includes: forming a first pad including a first metal and an inter-connection line including the first metal in a scribe lane region; forming a second pad including the first metal in a chip region; sequentially forming an etch-stop layer and a first insulation layer on the first pad, the inter-connection line, and the second pad; exposing the first and second pads by patterning the etch-stop layer and the first insulation layer; forming third and fourth pads including a second metal on the first and second pads; sequentially forming second and third insulation layers on the third pad, the fourth pad, and the patterned first insulation layer; and etching the first, second, and third insulation layers using the patterned photosensitive layer on the third insulation layer to expose the third and fourth pads.

Abstract: Disclosed is a method of fabricating a CMOS (Complementary Metal Oxide Silicon) image sensor. The method includes the steps of: forming a device protective layer and a metal interconnection on a substrate formed with a light receiving device; forming an inner micro-lens on the metal interconnection; coating an interlayer dielectric layer on the inner micro-lens and then forming a color filter; and forming an outer micro-lens including a planarization layer and photoresist on the color filter. The inner micro-lens is formed by depositing the outer layer on dome-shaped photoresist. The curvature radius of the inner micro-lens is precisely and uniformly maintained and the inner micro-lens is easily formed while improving the light efficiency. Since the fabrication process for the CMOS image sensor is simplified, the product yield is improved and the manufacturing cost is reduced.

Abstract: Disclosed are a CMOS image sensor and a method for manufacturing the same, capable of improving the characteristics of the image sensor by increasing junction capacitance of a floating diffusion area. The CMOS image sensor generally includes a photodiode and a plurality of transistors (e.g., transfer, reset, drive, and select transistors), a first conductive type semiconductor substrate, having an active area including a photodiode area, a floating diffusion area, and a voltage input/output area, a gate electrode of each transistor on the active area, a first conductive type first well area in the semiconductor substrate corresponding to the voltage input/output area, a first conductive type second well area in the semiconductor substrate corresponding to the floating diffusion area, and a second conductive type diffusion area in the semiconductor substrate at opposed sides of each gate electrode.

Abstract: An interconnection line of a semiconductor device and a method of forming the same using a dual damascene process are disclosed. An example interconnection line of a semiconductor device includes a semiconductor substrate, a first interconnection line formed on the substrate, an insulating layer pattern formed on the substrate to expose a portion of the first interconnection line, and a metal pad layer formed on the exposed portion of the first interconnection line. The example interconnection line also includes an intermediate insulating layer formed on the entire surface of the substrate and having a via hole and a trench exposing the metal pad layer, and a second interconnection formed in the via hole and the trench and electrically connected to the first interconnection line through the metal pad layer.

Abstract: Disclosed are a capacitor of a semiconductor device and a method of fabricating the same. The capacitor includes a capacitor top electrode, a capacitor bottom electrode aligned with a bottom surface and three lateral sides of the capacitor top electrode, and a capacitor insulating layer between the capacitor top electrode and the capacitor bottom electrode.

Abstract: Provided are a flash memory and a method for manufacturing the same. The flash memory includes a semiconductor substrate having a device isolation region and an active region; a stacked gate on the semiconductor substrate; an insulation layer covering the semiconductor substrate and the stacked gate; a drain contact penetrating the insulation layer on one side of the stacked gate; and a source line penetrating the insulation layer on an opposite side of the stacked gate.

Abstract: A flash memory device, and a manufacturing method thereof, having advantages of protecting sidewalls of a floating gate and a control gate and preventing a recess of an active area of a source region are provided. The method includes forming a tunneling oxide layer on an active region of a semiconductor substrate, forming a floating gate, a gate insulation layer, and a control gate on the tunneling oxide layer, forming insulation sidewall spacers on sides of the floating gate and the control gate, and removing at least portions of the tunneling oxide layer and the device isolation layer so as to expose the active region.

Abstract: A split gate (flash) EEPROM cell and a method for manufacturing the same is disclosed, in which a control gate and a floating gate are formed in a vertical structure, to minimize a size of the cell, to obtain a high coupling ratio, and to lower a programming voltage. The split gate EEPROM cell includes a semiconductor substrate having a trench; a tunneling oxide layer at sidewalls of the trench; a floating gate, a dielectric layer and a control gate in sequence on the tunneling oxide layer; a buffer dielectric layer at sidewalls of the floating gate and the control gate; a source junction in the semiconductor substrate at the bottom surface of the trench; a source electrode in the trench between opposing buffer dielectric layers, electrically connected to the source junction; and a drain junction on the surface of the semiconductor substrate outside the trench.

Abstract: Disclosed are a power semiconductor device and a method for manufacturing the same. The power semiconductor device has a PIP capacitor and an LDMOS transistor, the LDMOS transistor having second and third gate electrodes separate from a first gate electrode, which may be formed in the process of forming the upper electrode of the PIP capacitor, so it is possible to realize an LDMOS having a higher breakdown voltage and lower Ron and Rsp without additional processing. A drain voltage, which may be different from a voltage applied to the first gate electrode, may be applied to the third gate electrode, so it is possible to realize an LDMOS having a high breakdown voltage and low Ron and Rsp.