Patents Assigned to Dongbu Electronics Co., Ltd.
  • Patent number: 7910466
    Abstract: A high-voltage semiconductor device and a method for making the same are provided. A high-voltage semiconductor device and a low-voltage semiconductor device are formed in a single substrate, a photolithography process that is required to form a high-voltage well region is omitted, and the well region of the high-voltage semiconductor is formed together with the well region of the low-voltage semiconductor device formed in another photolithography process.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: March 22, 2011
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Choul Joo Ko
  • Patent number: 7906399
    Abstract: Disclosed is a semiconductor transistor for enhancing performance of PMOS and NMOS transistors, particularly current driving performance, while reducing a narrow width effect. A narrow width MOS transistor includes: a channel of which width is W0 and length is L0; an active area including source and drain areas formed at both sides with the channel as a center; a gate insulating layer formed on the channel; a gate conductor formed on the gate insulating layer and intersecting the active area; a first additional active area of width is larger than that W0 of the channel as an active area added to the source area; and a second additional active area of width is larger than that W0 of the channel as an active area added to the drain area. When the structure of the transistor having the additional active areas is applied to NMOS and PMOS transistors, a driving current is represented as 107.27% and 103.31%, respectively. Accordingly, the driving currents of both PMOS and NMOS transistors are enhanced.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: March 15, 2011
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Jung Ho Ahn
  • Patent number: 7893437
    Abstract: A semiconductor device and method of manufacturing the same are disclosed. An example semiconductor device includes a semiconductor substrate having a first well, a first source electrode, a drain electrode, and a first gate insulation layer formed on the semiconductor substrate, and a gate electrode formed on the first gate insulation layer. The example device also includes a second gate insulation layer formed on the gate electrode, a first source region formed on the semiconductor substrate between the first source electrode and the first gate insulation layer, a first drain region formed on the semiconductor substrate between the drain electrode and the first gate insulation layer, an insulating layer formed on the first source electrode, on the first source region, and on the first drain region, and a second source electrode formed on the insulating layer over the first source electrode.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: February 22, 2011
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Sang-Hyun Ban
  • Patent number: 7883966
    Abstract: A split gate (flash) EEPROM cell and a method for manufacturing the same is disclosed, in which a control gate and a floating gate are formed in a vertical structure, to minimize a size of the cell, to obtain a high coupling ratio, and to lower a programming voltage. The split gate EEPROM cell includes a semiconductor substrate having a trench; a tunneling oxide layer at sidewalls of the trench; a floating gate, a dielectric layer and a control gate in sequence on the tunneling oxide layer; a buffer dielectric layer at sidewalls of the floating gate and the control gate; a source junction in the semiconductor substrate at the bottom surface of the trench; a source electrode in the trench between opposing buffer dielectric layers, electrically connected to the source junction; and a drain junction on the surface of the semiconductor substrate outside the trench.
    Type: Grant
    Filed: August 27, 2009
    Date of Patent: February 8, 2011
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Heung Jin Kim
  • Patent number: 7883971
    Abstract: Disclosed are a gate structure in a trench region of a semiconductor device and a method for manufacturing the same. The semiconductor device includes a pair of drift regions formed in a semiconductor substrate; a trench region formed between the pair of drift regions; an oxide layer spacer on sidewalls of the trench region; a gate formed in the trench region; and a source and a drain formed in the pair of the drift regions, respectively.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: February 8, 2011
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Kwang Young Ko
  • Patent number: 7875524
    Abstract: The inductor for a semiconductor device includes at least one dielectric pattern selectively formed on a top of the interlayer dielectric, at least one first metal wire formed on a top of the interlayer dielectric, at least one second metal wire formed on a top of the dielectric pattern, and an upper protective film formed on the top of the interlayer dielectric to completely cover the first and second metal wires, wherein the first and second metal wires are alternately arranged at different vertical locations and are formed in a spiral configuration.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: January 25, 2011
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Nam Joo Kim
  • Patent number: 7868368
    Abstract: A CMOS image sensor and a method for manufacturing the same are provided. The CMOS image sensor enlarges an area of a real image and prevents interference between adjacent pixels by forming a plurality of microlenses on a convex surface and forming a light blocking layer in the space between each of color filters. The CMOS image sensor can include photodiodes, a first planarization layer, R, G, B color filter layers, a second planarization layer having holes filled with a light blocking layer, and a plurality of microlenses.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: January 11, 2011
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Dong Bin Park
  • Patent number: 7838319
    Abstract: There are provided a MOS transistor and a manufacturing method thereof. The MOS transistor includes a substrate on which an insulating layer is formed, a gate embedded in the insulating layer, wherein the top surface of the gate is exposed, a gate oxide layer formed on the insulating layer and the gate, a silicon layer formed on the gate oxide layer, and a source region and a drain region formed in the silicon layer to be in contact with the gate oxide layer.
    Type: Grant
    Filed: November 3, 2008
    Date of Patent: November 23, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Yun Hyung Sun
  • Patent number: 7839006
    Abstract: A semiconductor device and a method for manufacturing the same prevents copper from being exposed to a surface of a passivation film after a copper metal line formation, to avoid contamination of processing equipment and the process environment. The method includes providing a substrate with a scribe lane and a chip area in which metal wiring layers are formed, forming a dielectric film, forming a conductive film on the dielectric film in a chip area and an alignment mark on the dielectric film in a scribe lane, forming passivation films, exposing the conductive film by removing the passivation films in a bonding pad portion in a chip area, forming another conductive film in the bonding pad portion to electrically connect with the conductive film, forming another passivation film, and selectively removing the passivation films.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: November 23, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Yung Pil Kim
  • Patent number: 7838934
    Abstract: A semiconductor device and a method for manufacturing the same are disclosed, in which an insulating layer may be formed in a strained silicon layer under source/drain regions to substantially overcome conventional problems resulting from a channel decrease in the semiconductor device.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: November 23, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Myung Jin Jung
  • Patent number: 7838413
    Abstract: Disclosed is a method of manufacturing a phase-change memory in which the lower electrode of the phase-change memory device is formed using barrier metal for forming a metal interconnection and a via in damascene and dual damascene processes. The method includes the steps of patterning an insulating layer on a semiconductor substrate, sequentially forming barrier metal and metal on the patterned insulating layer, polishing the metal by a CMP process to planarize the metal and patterning the planarized barrier metal to a lower electrode of a desired phase-change memory device, depositing an insulating layer on the patterned lower electrode, forming a hole in the deposited insulating layer, and forming an upper electrode on the resultant material to pattern the upper electrode, and depositing an insulating layer on the upper electrode and forming a via for connecting a metal interconnection and the lower electrode to each other. Therefore, additional deposition for forming the lower electrode is not necessary.
    Type: Grant
    Filed: December 26, 2006
    Date of Patent: November 23, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Kun Hyuk Lee
  • Patent number: 7838917
    Abstract: A CMOS image sensor and method for fabricating the same, wherein the CMOS image sensor has minimized dark current at the boundary area between a photodiode and an isolation layer. The present invention includes a first-conductivity-type doping area formed in the device isolation area of the substrate, the first-conductivity-type doping area surrounding the isolation area and a dielectric layer formed between the isolation layer and the first-conductivity-type doping area, wherein the first-conductivity-type doping area and the dielectric layer are located between the isolation layer and a second-conductivity-type diffusion area.
    Type: Grant
    Filed: February 12, 2009
    Date of Patent: November 23, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Chang Hun Han
  • Patent number: 7833857
    Abstract: An ESD protecting circuit and a manufacturing method thereof are provided. The ESD protecting circuit includes a device isolation layer, first and second high-concentration impurity regions, a third high-concentration impurity region of a complementary type, first and second conductive wells, and a fourth conductive impurity region. The ESD protecting circuit is configured as a field transistor without a gate electrode, and the high breakdown voltage characteristics of the field transistor are lowered by implanting impurity ions, providing an ESD protecting circuit with a low breakdown voltage and low leakage current. Because the leakage current is reduced, the ESD protecting circuit can be used for an analog I/O device that is sensitive to current fluxes. Also, an N-type well may protect a junction of the field transistor.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: November 16, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: San Hong Kim
  • Patent number: 7816259
    Abstract: Deterioration of yield may be prevented when a contact in a semiconductor device is made by a method including forming a contact hole by selectively removing an insulating layer from a semiconductor substrate, depositing a barrier layer on the insulating layer and on the surface of (or in) the contact hole, depositing an initial tungsten layer on the barrier layer to at least a predetermined thickness, removing particles generated during at least one of the depositing steps, and filling the contact hole with an additional tungsten layer.
    Type: Grant
    Filed: October 24, 2005
    Date of Patent: October 19, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Bo-Yeoun Jo
  • Patent number: 7811928
    Abstract: Semiconductor devices and methods of fabricating semiconductor devices are disclosed. A disclosed semiconductor device includes a silicon substrate, a source region and a drain region. A gate electrode is formed on the silicon substrate. Also, a metal silicide layer is formed on each of the gate electrode, the source region, and the drain region. The metal silicide layer has a thickness uniformity of about 1˜20%. A disclosed fabrication method includes forming a metal layer on a silicon substrate having a gate electrode, a source region, and a drain region; performing a plasma treatment on the metal layer; forming a protective layer on the metal layer; and heat treating the silicon substrate on which the protective layer is formed to thereby form a metal silicide layer. A gas that includes nitrogen is used as a plasma gas during the plasma treatment.
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: October 12, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventors: Han-Choon Lee, Jin-Woo Park
  • Patent number: 7811894
    Abstract: An improved bipolar junction transistor and a method for manufacturing the same are provided. The bipolar junction transistor includes: a buried layer and a high concentration N-type collector region in a P-type semiconductor substrate; a low concentration P-type base region in the semiconductor substrate above the buried layer; a first high concentration P-type base region along an edge of the low concentration P-type base region; a second high concentration P-type base region at a center of the low concentration P-type base region; a high concentration N-type emitter region between the first and second high concentration base regions; and insulating layer spacers between the high concentration base regions and the high concentration emitter regions. In the bipolar junction transistor, the emitter-base distance can be reduced using a trench and an insulating layer spacer. This may improve base voltage and high-speed response characteristics.
    Type: Grant
    Filed: May 11, 2009
    Date of Patent: October 12, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Nam Joo Kim
  • Patent number: 7807996
    Abstract: The test pattern according to the present invention consists of an opaque metal film pattern formed on a semiconductor substrate, an insulating film formed on the semiconductor substrate and the metal film pattern, a red color filter formed on the insulating film, a planarization layer formed on the insulating film and the red color filter, and a number of micro-lenses formed on the planarization layer.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: October 5, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventors: Eun Sang Cho, Kee Ho Kim
  • Patent number: 7795084
    Abstract: Semiconductor devices and a fabricating method therefore are disclosed.
    Type: Grant
    Filed: October 9, 2009
    Date of Patent: September 14, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Jin Hyo Jung
  • Patent number: 7790605
    Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate including a conducting layer, a first insulating film formed on the semiconductor substrate and having a via hole formed therein, a lower barrier film formed on an inside wall of the via hole, a first metal wiring formed on the lower barrier film, a second insulating film formed on the first metal wiring and the first insulating film, the second insulating film being provided with a trench which has a width greater than a width of the via hole, an upper barrier film formed on a lower surface of the trench, a second metal wiring formed on the upper barrier film, and a sidewall barrier film formed on sidewalls of the upper barrier film and the second metal wiring. The sidewall barrier film has an L-shaped mirror-symmetrical structure.
    Type: Grant
    Filed: December 26, 2006
    Date of Patent: September 7, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Jae-Won Han
  • Patent number: 7790547
    Abstract: A method and non-volatile memory device are provided that are characterized by ion-implantation of impurities in the sidewalls of a first electrode. The inclusion of impurities in the sidewalls eliminates geometric abnormalities, referred to herein as a bird's beak, in the first electrode, which are caused by numerous oxidation processes being performed in the overall memory fabrication process. By eliminating these geometric abnormalities, thickening of the block oxide layer proximate the area of geometric abnormalities does not occurring, resulting in a memory device capable of efficiently programming and erasing data.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: September 7, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Jin Hyo Jung